\n

HDIV

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected

Registers

HDIV_DIVIDEND (DIVIDEND)

HDIV_STATUS (STATUS)

HDIV_DIVISOR (DIVISOR)

HDIV_QUOTIENT (QUOTIENT)

HDIV_REM (REM)


HDIV_DIVIDEND (DIVIDEND)

Dividend Source Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HDIV_DIVIDEND HDIV_DIVIDEND read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVIDEND

DIVIDEND : Dividend Source\nThis register is given the dividend of divider before calculation starting.
bits : 0 - 31 (32 bit)
access : read-write


HDIV_STATUS (STATUS)

Divider Status Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HDIV_STATUS HDIV_STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVBYZERO

DIVBYZERO : Divisor Zero Warning\nNote: The DIVBYZERO flag is used to indicate divide-by-zero situation and updated whenever HDIV_DIVISOR is written. This register is read only.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

The divisor is not 0

#1 : 1

The divisor is 0

End of enumeration elements list.


HDIV_DIVISOR (DIVISOR)

Divisor Source Resister
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HDIV_DIVISOR HDIV_DIVISOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVISOR

DIVISOR : Divisor Source\nThis register is given the divisor of divider before calculation starts.\nNote: When this register is written, hardware divider will start calculate.
bits : 0 - 15 (16 bit)
access : read-write


HDIV_QUOTIENT (QUOTIENT)

Quotient Result Resister
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HDIV_QUOTIENT HDIV_QUOTIENT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QUOTIENT

QUOTIENT : Quotient Result\nThis register holds the quotient result of divider after calculation complete.
bits : 0 - 31 (32 bit)
access : read-write


HDIV_REM (REM)

Remainder Result Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HDIV_REM HDIV_REM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REM

REM : Remainder Result\nThe remainder of hardware divider is 16-bit sign integer (REM[15:0]) with sign extension (REM[31:16]) to 32-bit integer.
bits : 0 - 31 (32 bit)
access : read-write



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