I2C_CTL (CTL)

I2C_CLKDIV (CLKDIV)

I2C_TOCTL (TOCTL)

I2C_ADDR1 (ADDR1)

I2C_ADDR2 (ADDR2)

I2C_ADDR3 (ADDR3)

I2C_ADDRMSK0 (ADDRMSK0)

I2C_ADDRMSK1 (ADDRMSK1)

I2C_ADDRMSK2 (ADDRMSK2)

I2C_ADDRMSK3 (ADDRMSK3)

I2C_CTL1 (CTL1)

I2C_ADDR0 (ADDR0)

I2C_STATUS1 (STATUS1)

I2C_DAT (DAT)

I2C_STATUS (STATUS)

AA : Assert Acknowledge Control Bit
bits : 2 - 2 (1 bit)
access : read-write

SI : I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware, and if bit INTEN (I2C_CTL[7]) is set, the I2C interrupt is requested. SI must be cleared by software. Software can write 1 to clear this bit.
bits : 3 - 3 (1 bit)
access : read-write

STO : I2C STOP Control Bit In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In Slave mode, setting STO resets I2C hardware to the defined not addressed Slave mode. This means it is NO LONGER in the Slave receiver mode to receive data from the master transmit device.
bits : 4 - 4 (1 bit)
access : read-write

STA : I2C START Control Bit\nSetting STA to logic 1 to enter Master mode. I2C hardware sends a START or repeats the START condition to bus when the bus is free.
bits : 5 - 5 (1 bit)
access : read-write

I2CEN : I2C Controller Enable Bit
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTEN : Enable Interrupt
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIVIDER : I2C Clock Divided Register\nNote: The minimum value of DIVIDER is 4.
bits : 0 - 7 (8 bit)
access : read-write

TOIF : Time-Out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

TOCDIV4 : Time-Out Counter Input Clock Divided By 4 Note: When enabled, the time-out period is extended 4 times.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TOCEN : Time-Out Counter Enabled\nNote: When the 14-bit time-out counter is enabled, it will start counting when SI is clear. Setting 1to the SI flag will reset counter and re-start up counting after SI is cleared.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADDRMSK : I2C Address Mask Register
bits : 1 - 7 (7 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKEN : Wake-Up Enable\nThe system can be wake up by I2C bus when the system is set into power mode and the received data matched one of the addresses in Address Register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FIFOEN : FIFO Mode Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NSTRETCH : NO STRETCH The I2C BUS
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OVIEN : I2C OVER RUN Interrupt Control Bit Setting OVIEN to enable will send a interrupt to system when the TWOFF bit is enabled and there is over run event in received FIFO.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

URIEN : I2C UNDER RUN Interrupt Control Bit\nSetting URIEN to enable will send a interrupt to system when the TWOFF bit is enabled and there is under run event happened in transmitted FIFO.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GC : General Call Function
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADDR : I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode, the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched.
bits : 1 - 7 (7 bit)
access : read-write

WKIF : I2C Wake-Up Interrupt Flag\nWhen chip is woken up from Power-Down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

FULL : I2C TWO LEVEL FIFO FULL
bits : 1 - 1 (1 bit)
access : read-write

EMPTY : I2C TWO LEVEL FIFO EMPTY
bits : 2 - 2 (1 bit)
access : read-write

OVIF : I2C OVER RUN Status Bit
bits : 3 - 3 (1 bit)
access : read-write

URIF : I2C UNDER RUN Status Bit
bits : 4 - 4 (1 bit)
access : read-write

DAT : I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of the I2C serial port.
bits : 0 - 7 (8 bit)
access : read-write

STATUS : I2C Status Register
bits : 0 - 7 (8 bit)
access : read-only