PWM_CLKPSC (CLKPSC)

PWM_PERIOD1 (PERIOD1)

PWM_PERIOD2 (PERIOD2)

PWM_PERIOD3 (PERIOD3)

PWM_PERIOD4 (PERIOD4)

PWM_PERIOD5 (PERIOD5)

PWM_CMPDAT0 (CMPDAT0)

PWM_CMPDAT1 (CMPDAT1)

PWM_CMPDAT2 (CMPDAT2)

PWM_CMPDAT3 (CMPDAT3)

PWM_CMPDAT4 (CMPDAT4)

PWM_CMPDAT5 (CMPDAT5)

PWM_CLKDIV (CLKDIV)

PWM_INTEN (INTEN)

PWM_INTSTS (INTSTS)

PWM_POEN (POEN)

PWM_BRKCTL (BRKCTL)

PWM_DTCTL (DTCTL)

PWM_ADCTCTL0 (ADCTCTL0)

PWM_ADCTCTL1 (ADCTCTL1)

PWM_ADCTSTS0 (ADCTSTS0)

PWM_ADCTSTS1 (ADCTSTS1)

PWM_PHCHG (PHCHG)

PWM_PHCHGNXT (PHCHGNXT)

PWM_CTL (CTL)

PWM_PHCHGMSK (PHCHGMSK)

PWM_IFA (IFA)

PWM_PERIOD0 (PERIOD0)

CLKPSC01 : Clock Prescaler 0 For PWM Counter 0 And 1 Clock input is divided by (CLKPSC01 + 1) before it is fed to the corresponding PWM counter.
bits : 0 - 7 (8 bit)
access : read-write

CLKPSC23 : Clock Prescaler 2 For PWM Counter 2 And 3\nClock input is divided by (CLKPSC23 + 1) before it is fed to the corresponding PWM counter.
bits : 8 - 15 (8 bit)
access : read-write

CLKPSC45 : Clock Prescaler 4 For PWM Counter 4 And 5\nClock input is divided by (CLKPSC45 + 1) before it is fed to the corresponding PWM counter.
bits : 16 - 23 (8 bit)
access : read-write

CMP : PWM Comparator Register\nCMP determines the PWM duty.\nEdge-aligned mode:\nNote: Any write to CMP will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write

CMPD : PWM Comparator Register For Down Counter In Center-Aligned Asymmetric Mode\nOthers: PWM output is always high
bits : 16 - 31 (16 bit)
access : read-write

CLKDIV0 : Timer 0 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CLKDIV5.)
bits : 0 - 2 (3 bit)
access : read-write

CLKDIV1 : Timer 1 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CLKDIV5.)
bits : 4 - 6 (3 bit)
access : read-write

CLKDIV2 : Timer 2 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CLKDIV5.)
bits : 8 - 10 (3 bit)
access : read-write

CLKDIV3 : Timer 3 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CLKDIV5.)
bits : 12 - 14 (3 bit)
access : read-write

CLKDIV4 : Timer 4 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CLKDIV5.)
bits : 16 - 18 (3 bit)
access : read-write

CLKDIV5 : Timer 5 Clock Source Selection\nSelect clock input for PWM timer.
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ZIEN0 : PWM Channel 0 Period Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ZIEN1 : PWM Channel 1 Period Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ZIEN2 : PWM Channel 2 Period Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ZIEN3 : PWM Channel 3 Period Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ZIEN4 : PWM Channel 4 Period Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ZIEN5 : PWM Channel 5 Period Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPDIEN0 : PWM Channel 0 Duty Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPDIEN1 : PWM Channel 1 Duty Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPDIEN2 : PWM Channel 2 Duty Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPDIEN3 : PWM Channel 3 Duty Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPDIEN4 : PWM Channel 4 Duty Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPDIEN5 : PWM Channel 5 Duty Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRKIEN : Enable Fault Brake0 And 1 Interrupt
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PINTTYPE : PWM Period Interrupt Type Selection\nNote: This bit is effective when PWM in central align mode only.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PIEN0 : PWM Channel 0 Central Interrupt Enable
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PIEN1 : PWM Channel 1 Central Interrupt Enable
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PIEN2 : PWM Channel 2 Central Interrupt Enable
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PIEN3 : PWM Channel 3 Central Interrupt Enable
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PIEN4 : PWM Channel 4 Central Interrupt Enable
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PIEN5 : PWM Channel 5 Central Interrupt Enable
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPUIEN0 : PWM Channel 0 Rising Interrupt Enable
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPUIEN1 : PWM Channel 1 Rising Interrupt Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPUIEN2 : PWM Channel 2 Rising Interrupt Enable
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPUIEN3 : PWM Channel 3 Rising Interrupt Enable
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPUIEN4 : PWM Channel 4 Rising Interrupt Enable
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPUIEN5 : PWM Channel 5 Rising Interrupt Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ZIF0 : PWM Channel 0 Period Interrupt Flag\nFlag is set by hardware when PWM0 down counter reaches zero. \nNote: Software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

ZIF1 : PWM Channel 1 Period Interrupt Flag\nFlag is set by hardware when PWM1 down counter reaches zero. \nNote: Software can write 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write

ZIF2 : PWM Channel 2 Period Interrupt Flag\nFlag is set by hardware when PWM2 down counter reaches zero. \nNote: Software can write 1 to clear this bit.
bits : 2 - 2 (1 bit)
access : read-write

ZIF3 : PWM Channel 3 Period Interrupt Flag\nFlag is set by hardware when PWM3 down counter reaches zero. \nNote: Software can write 1 to clear this bit.
bits : 3 - 3 (1 bit)
access : read-write

ZIF4 : PWM Channel 4 Period Interrupt Flag\nFlag is set by hardware when PWM4 down counter reaches zero. \nNote: Software can write 1 to clear this bit.
bits : 4 - 4 (1 bit)
access : read-write

ZIF5 : PWM Channel 5 Period Interrupt Flag\nFlag is set by hardware when PWM5 down counter reaches zero. \nNote: Software can write 1 to clear this bit.
bits : 5 - 5 (1 bit)
access : read-write

CMPDIF0 : PWM Channel 0 Duty Interrupt Flag\nFlag is set by hardware when a channel 0 PWM counter reaches PWM_CMPDAT0 in down-count direction. \nNote: Software can write 1 to clear this bit.
bits : 8 - 8 (1 bit)
access : read-write

CMPDIF1 : PWM Channel 1 Duty Interrupt Flag\nFlag is set by hardware when a channel 1 PWM counter reaches PWM_CMPDAT1 in down-count direction. \nNote: Software can write 1 to clear this bit.
bits : 9 - 9 (1 bit)
access : read-write

CMPDIF2 : PWM Channel 2 Duty Interrupt Flag\nFlag is set by hardware when a channel 2 PWM counter reaches PWM_CMPDAT2 in down-count direction. \nNote: Software can write 1 to clear this bit.
bits : 10 - 10 (1 bit)
access : read-write

CMPDIF3 : PWM Channel 3 Duty Interrupt Flag\nFlag is set by hardware when a channel 3 PWM counter reaches PWM_CMPDAT3 in down-count direction. \nNote: Software can write 1 to clear this bit.
bits : 11 - 11 (1 bit)
access : read-write

CMPDIF4 : PWM Channel 4 Duty Interrupt Flag\nFlag is set by hardware when a channel 4 PWM counter reaches PWM_CMPDAT4 in down-count direction. \nNote: Software can write 1 to clear this bit.
bits : 12 - 12 (1 bit)
access : read-write

CMPDIF5 : PWM Channel 5 Duty Interrupt Flag\nFlag is set by hardware when a channel 5 PWM counter reaches PWM_CMPDAT5 in down-count direction. \nNote: Software can write 1 to clear this bit.
bits : 13 - 13 (1 bit)
access : read-write

BRKIF0 : PWM Brake0 Flag\nNote: Software can write 1 to clear this bit.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRKIF1 : PWM Brake1 Flag\nNote: Software can write 1 to clear this bit.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PIF0 : PWM Channel 0 Center Interrupt Flag\nFlag is set by hardware when a channel 0 PWM rise counter reaches CNT0. Software can write 1 to clear this bit.
bits : 18 - 18 (1 bit)
access : read-write

PIF1 : PWM Channel 1 Center Interrupt Flag\nFlag is set by hardware when a channel 1 PWM rise counter reaches CNT1. Software can write 1 to clear this bit.
bits : 19 - 19 (1 bit)
access : read-write

PIF2 : PWM Channel 2 Center Interrupt Flag\nFlag is set by hardware when a channel 2 PWM rise counter reaches CNT2. Software can write 1 to clear this bit.
bits : 20 - 20 (1 bit)
access : read-write

PIF3 : PWM Channel 3 Center Interrupt Flag\nFlag is set by hardware when a channel 3 PWM rise counter reaches CNT3. Software can write 1 to clear this bit.
bits : 21 - 21 (1 bit)
access : read-write

PIF4 : PWM Channel 4 Center Interrupt Flag\nFlag is set by hardware when a channel 4 PWM rise counter reaches CNT4. Software can write 1 to clear this bit.
bits : 22 - 22 (1 bit)
access : read-write

PIF5 : PWM Channel 5 Center Interrupt Flag\nFlag is set by hardware when a channel 5 PWM rise counter reaches CNT5. Software can write 1 to clear this bit.
bits : 23 - 23 (1 bit)
access : read-write

CMPUIF0 : PWM Channel 1 Rise Interrupt Flag\nFlag is set by hardware when a channel 0 PWM rise counter reaches PWM_CMPDAT0. Software can write 1 to clear this bit.
bits : 24 - 24 (1 bit)
access : read-write

CMPUIF1 : PWM Channel 1 Rise Interrupt Flag\nFlag is set by hardware when a channel 1 PWM rise counter reaches PWM_CMPDAT1. Software can write 1 to clear this bit.
bits : 25 - 25 (1 bit)
access : read-write

CMPUIF2 : PWM Channel 2 Rise Interrupt Flag\nFlag is set by hardware when a channel 2 PWM rise counter reaches PWM_CMPDAT2. Software can write 1 to clear this bit.
bits : 26 - 26 (1 bit)
access : read-write

CMPUIF3 : PWM Channel 3 Rise Interrupt Flag\nFlag is set by hardware when a channel 3 PWM rise counter reaches PWM_CMPDAT3. Software can write 1 to clear this bit.
bits : 27 - 27 (1 bit)
access : read-write

CMPUIF4 : PWM Channel 4 Rise Interrupt Flag\nFlag is set by hardware when a channel 4 PWM rise counter reaches PWM_CMPDAT4. Software can write 1 to clear this bit.
bits : 28 - 28 (1 bit)
access : read-write

CMPUIF5 : PWM Channel 5 Rise Interrupt Flag\nFlag is set by hardware when a channel 5 PWM rise counter reaches \nPWM_CNT0\n5. Software can write 1 to clear this bit.
bits : 29 - 29 (1 bit)
access : read-write

POEN0 : PWM Channel 0 Output Enable Register\nNote: The corresponding GPIO pin must be switched to PWM function.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POEN1 : PWM Channel 1 Output Enable Register\nNote: The corresponding GPIO pin must be switched to PWM function.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POEN2 : PWM Channel 2 Output Enable Register\nNote: The corresponding GPIO pin must be switched to PWM function.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POEN3 : PWM Channel 3 Output Enable Register\nNote: The corresponding GPIO pin must be switched to PWM function.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POEN4 : PWM Channel 4 Output Enable Register\nNote: The corresponding GPIO pin must be switched to PWM function.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POEN5 : PWM Channel 5 Output Enable Register\nNote: The corresponding GPIO pin must be switched to PWM function.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRK0EN : Enable BKP0 Pin Trigger Fault Brake Function 0
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRK1EN : Enable BKP1 Pin Trigger Fault Brake Function 1
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRK0SEL : BKP1 Fault Brake Function Source Selection
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRK1SEL : BKP0 Fault Brake Function Source Selection
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRKSTS : PWM Fault Brake Event Flag (Write 1 Clear)\nSoftware can write 1 to clear this bit and must clear this bit before restart PWM counter.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRKACT : PWM Brake Type
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SWBRK : Software Brake
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKOD0 : PWM Channel 0 Brake Output Select Register
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKOD1 : PWM Channel 1 Brake Output Select Register
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKOD2 : PWM Channel 2 Brake Output Select Register
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKOD3 : PWM Channel 3 Brake Output Select Register
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKOD4 : PWM Channel 4 Brake Output Select Register
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKOD5 : PWM Channel 5 Brake Output Select Register
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

D6BKOD : D6 Brake Output Select Register
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

D7BKOD : D7 Brake Output Select Register
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DTCNT01 : Dead-Zone Interval Register For Pair Of Channel0 And Channel1 (PWM0 And PWM1 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding CLKDIV bits.
bits : 0 - 7 (8 bit)
access : read-write

DTCNT23 : Dead-Zone Interval Register For Pair Of Channel2 And Channel3 (PWM2 And PWM3 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding CLKDIV bits.
bits : 8 - 15 (8 bit)
access : read-write

DTCNT45 : Dead-Zone Interval Register For Pair Of Channel4 And Channel5 (PWM4 And PWM5 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding CLKDIV bits.
bits : 16 - 23 (8 bit)
access : read-write

CUTRGEN0 : PWM Channel 0 Compare Up Count Point Trigger ADC Enable Bit \nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPTRGEN0 : PWM Channel 0 Center Point Trigger ADC Enable Bit \nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CDTRGEN0 : PWM Channel 0 Compare Down Count Point Trigger ADC Enable Bit\nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ZPTRGEN0 : PWM Channel 0 Zero Point Trigger ADC Enable Bit\nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CUTRGEN1 : PWM Channel 1 Compare Up Count Point Trigger ADC Enable Bit \nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPTRGEN1 : Note: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CDTRGEN1 : PWM Channel 1 Compare Down Count Point Trigger ADC Enable Bit \nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ZPTRGEN1 : PWM Channel 1 Zero Point Trigger ADC Enable Bit \nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CUTRGEN2 : PWM Channel 2 Compare Up Count Point Trigger ADC Enable Bit \nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPTRGEN2 : PWM Channel 2 Center Point Trigger ADC Enable Bit \nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CDTRGEN2 : PWM Channel 2 Compare Down Count Point Trigger ADC Enable Bit \nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ZPTRGEN2 : PWM Channel 2 Zero Point Trigger ADC Enable Bit \nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CUTRGEN3 : PWM Channel 3 Compare Up Count Point Trigger ADC Enable Bit \nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPTRGEN3 : PWM Channel 3 Center Point Trigger ADC Enable Bit \nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CDTRGEN3 : PWM Channel 3 Compare Down Count Point Trigger ADC Enable Bit \nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ZPTRGEN3 : PWM Channel 3 Zero Point Trigger ADC Enable Bit \nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CUTRGEN4 : PWM Channel 4 Compare Up Count Point Trigger ADC Enable Bit\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPTRGEN4 : PWM Channel 4 Center Point Trigger ADC Enable Bit\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CDTRGEN4 : PWM Channel 4 Compare Down Count Point Trigger ADC Enable Bit\nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ZPTRGEN4 : PWM Channel 4 Zero Point Trigger ADC Enable Bit\nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CUTRGEN5 : PWM Channel 5 Compare Up Count Point Trigger ADC Enable Bit\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPTRGEN5 : PWM Channel 5 Center Point Trigger ADC Enable Bit\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CDTRGEN5 : PWM Channel 5 Compare Down Count Point Trigger ADC Enable Bit\nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ZPTRGEN5 : PWM Channel 5 Zero Point Trigger ADC Enable Bit\nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CUTRGF0 : PWM Channel 0 Zero Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

CPTRGF0 : PWM Channel 0 Compare Down Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write

CDTRGF0 : PWM Channel 0 Center Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit.
bits : 2 - 2 (1 bit)
access : read-write

ZPTRGF0 : PWM Channel 0 Compare Up Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit.
bits : 3 - 3 (1 bit)
access : read-write

CUTRGF1 : PWM Channel 1 Zero Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit.
bits : 8 - 8 (1 bit)
access : read-write

CPTRGF1 : PWM Channel 1 Compare Down Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit.
bits : 9 - 9 (1 bit)
access : read-write

CDTRGF1 : PWM Channel 1 Center Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit.
bits : 10 - 10 (1 bit)
access : read-write

ZPTRGF1 : PWM Channel 1 Compare Up Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit.
bits : 11 - 11 (1 bit)
access : read-write

CUTRGF2 : PWM Channel 3 Zero Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit.
bits : 16 - 16 (1 bit)
access : read-write

CPTRGF2 : PWM Channel 2 Compare Down Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit.
bits : 17 - 17 (1 bit)
access : read-write

CDTRGF2 : PWM Channel 2 Center Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit.
bits : 18 - 18 (1 bit)
access : read-write

ZPTRGF2 : PWM Channel 2 Compare Up Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit.
bits : 19 - 19 (1 bit)
access : read-write

CUTRGF3 : PWM Channel 3 Zero Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit.
bits : 24 - 24 (1 bit)
access : read-write

CPTRGF3 : PWM Channel 3 Compare Down Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit.
bits : 25 - 25 (1 bit)
access : read-write

CDTRGF3 : PWM Channel 3 Center Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit.
bits : 26 - 26 (1 bit)
access : read-write

ZPTRGF3 : PWM Channel 3 Compare Up Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit.
bits : 27 - 27 (1 bit)
access : read-write

CUTRGF4 : PWM Channel 4 Zero Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

CPTRGF4 : PWM Channel 4 Compare Down Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write

CDTRGF4 : PWM Channel 4 Center Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit.
bits : 2 - 2 (1 bit)
access : read-write

ZPTRGF4 : PWM Channel 4 Compare Up Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit.
bits : 3 - 3 (1 bit)
access : read-write

CUTRGF5 : PWM Channel 5 Zero Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit.
bits : 8 - 8 (1 bit)
access : read-write

CPTRGF5 : PWM Channel 5 Compare Down Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit.
bits : 9 - 9 (1 bit)
access : read-write

CDTRGF5 : PWM Channel 5 Center Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit.
bits : 10 - 10 (1 bit)
access : read-write

ZPTRGF5 : PWM Channel 5 Compare Up Count Point Trigger ADC Flag\nNote: Software can write 1 to clear this bit.
bits : 11 - 11 (1 bit)
access : read-write

MSKDAT0 : MSKDAT0: When MSKEN0 Is Zero, Channel 0's Output Waveform Is MSKDAT0
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT1 : MSKDAT1: When MSKEN1is Zero, Channel 1's Output Waveform Is MSKDAT1
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT2 : MSKDAT2: When MSKEN2 Is Zero, Channel 2's Output Waveform Is MSKDAT2
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT3 : MSKDAT3: When MSKEN3 Is Zero, Channel 3's Output Waveform Is MSKDAT3
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT4 : MSKDAT4: When MSKEN4is Zero, Channel 4's Output Waveform Is MSKDAT4
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT5 : MSKDAT5: When MSKEN5 Is Zero, Channel 5's Output Waveform Is MSKDAT5
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT6 : MSKDAT6: When MSKEN6 Is 1, Channel 6's Output Waveform Is MSKDAT6
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT7 : MSKDAT7: When MSKEN7 Is 1, Channel 7's Output Waveform Is MSKDAT7
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKEN0 : MSKEN Channel 0 Output Enable Control
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKEN1 : MSKEN Channel 1 Output Enable Control
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKEN2 : MSKEN Channel 2 Output Enable Control
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKEN3 : MSKEN Channel 3 Output Enable Control
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKEN4 : MSKEN Channel 4 Output Enable Control
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKEN5 : MSKEN Channel 5 Output Enable Control
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AUTOCLR0 : Hardware Auto Clear ACMP0TEN When ACMP0 Trigger It
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AUTOCLR1 : Hardware Auto Clear ACMP1TEN When ACMP1 Trigger It
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OFFEN01 : Setting This Bit Will Force MSKEN0 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It This Feature Is Usually In Step Motor Application Note: only for MSKEN0, MSKEN3, MSKEN2, MSKEN3.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OFFEN11 : Setting This Bit Will Force MSKEN1 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It This Feature Is Usually In Step Motor Application Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OFFEN21 : Setting This Bit Will Force MSKEN2 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It This Feature Is Usually In Step Motor Application Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OFFEN31 : Setting This Bit Will Force MSKEN3 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It This Feature Is Usually In Step Motor Application Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

A1POSSEL : A1POSSEL\nSelect the positive input source of ACMP1.
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1TEN : Enable Timer1 Trigger PWM Function\nWhen this bit is set, timer1 time-out event will update PWM_PHCHG with PWM_PHCHG_NXT register.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACMP1TEN : Enable ACMP1 Trigger Function\nNote: This bit will be auto cleared when ACMP1 trigger PWM if AUTOCLR1 is set.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OFFEN00 : Setting This Bit Will Force MSKEN0 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It This Feature Is Usually In Step Motor Application Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OFFEN10 : Setting This Bit Will Force MSKEN1 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It This Feature Is Usually In Step Motor Application Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OFFEN20 : Setting This Bit Will Force MSKEN2 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It This Feature Is Usually In Step Motor Application Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OFFEN30 : Setting This Bit Will Force MSKEN3 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It This Feature Is Usually In Step Motor Application Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

A0POSSEL : A0POSSEL\nSelect the positive input source of ACMP0.
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

T0 : Enable Timer0 Trigger PWM Function\nWhen this bit is set, timer0 time-out event will update PWM_PHCHG with PWM_PHCHG_NXT register.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACMP0TEN : Enable ACMP0 Trigger Function\nNote: This bit will be auto cleared when ACMP0 trigger PWM if AUTOCLR0 is set.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT0 : MSKDAT0: When MSKEN0 Is Zero, Channel 0's Output Waveform Is MSKDAT0
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT1 : MSKDAT1: When MSKEN1is Zero, Channel 1's Output Waveform Is MSKDAT1
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT2 : MSKDAT2: When MSKEN2 Is Zero, Channel 2's Output Waveform Is MSKDAT2
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT3 : MSKDAT3: When MSKEN3 Is Zero, Channel 3's Output Waveform Is MSKDAT3
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT4 : MSKDAT4: When MSKEN4is Zero, Channel 4's Output Waveform Is MSKDAT4
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT5 : MSKDAT5: When MSKEN5 Is Zero, Channel 5's Output Waveform Is MSKDAT5
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT6 : MSKDAT6: When MSKEN6 Is 1, Channel 6's Output Waveform Is MSKDAT6
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT7 : MSKDAT7: When MSKEN7 Is 1, Channel 7's Output Waveform Is MSKDAT7
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKEN0 : MSKEN Channel 0 Output Enable Control
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKEN1 : MSKEN Channel 1 Output Enable Control
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKEN2 : MSKEN Channel 2 Output Enable Control
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKEN3 : MSKEN Channel 3 Output Enable Control
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKEN4 : MSKEN Channel 4 Output Enable Control
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKEN5 : MSKEN Channel 5 Output Enable Control
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AUTOCLR0 : Hardware Auto Clear ACMP0TEN When ACMP0 Trigger It
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AUTOCLR1 : Hardware Auto Clear ACMP1TEN When ACMP1 Trigger It
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OFFEN01 : Setting This Bit Will Force MSKEN0 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It This Feature Is Usually In Step Motor Application Note: only for MSKEN0, MSKEN3, MSKEN2, MSKEN3.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OFFEN11 : Setting This Bit Will Force MSKEN1 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It This Feature Is Usually In Step Motor Application Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OFFEN21 : Setting This Bit Will Force MSKEN2 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It This Feature Is Usually In Step Motor Application Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OFFEN31 : Setting This Bit Will Force MSKEN3to Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It This Feature Is Usually In Step Motor Application Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

A1POSSEL : A1POSSEL\nSelect the positive input source of ACMP1.
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1TEN : Enable Timer1 Trigger PWM Function\nWhen this bit is set, timer1 time-out event will update PWM_PHCHG with PWM_PHCHG_NXT register.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACMP1TEN : Enable ACMP1 Trigger Function\nNote: This bit will be auto cleared when ACMP1 trigger PWM if AUTOCLR1 is set.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OFFEN00 : Setting This Bit Will Force MSKEN0 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It This Feature Is Usually In Step Motor Application Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OFFEN10 : Setting This Bit Will Force MSKEN1 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It This Feature Is Usually In Step Motor Application Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OFFEN20 : Setting This Bit Will Force MSKEN2 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It This Feature Is Usually In Step Motor Application Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3..
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OFFEN30 : Setting This Bit Will Force MSKEN3 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It This Feature Is Usually In Step Motor Application Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

A0POSSEL : A0POSSEL\nSelect the positive input source of ACMP0.
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0TEN : Enable Timer0 Trigger PWM Function\nWhen this bit is set, timer0 time-out event will update PWM_PHCHG with PWM_PHCHG_NXT register.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACMP0TEN : Enable ACMP0 Trigger Function\nNote: This bit will be auto cleared when ACMP0 trigger PWM if AUTOCLR0 is set.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN0 : PWM-Timer 0 Enable/Disable Start Run
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBGTRIOFF : PWM Debug Mode Configuration Bit (Available In DEBUG Mode Only)
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PINV0 : PWM-Timer 0 Output Inverter Enabled/Disabled
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTMODE0 : PWM-Timer 0 Auto-Reload/One-Shot Mode\nNote: If there is a rising transition at this bit, it will cause PWM_PERIOD0 and PWM_CMPDAT0 cleared.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN1 : PWM-Timer 1 Enable/Disable Start Run
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HCUPDT : Half Cycle Update Enable For Center-Aligned Type
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PINV1 : PWM-Timer 1 Output Inverter Enabled/Disabled
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTMODE1 : PWM-Timer 1 Auto-Reload/One-Shot Mode\nNote: If there is a rising transition at this bit, it will cause PWM_PERIOD1 and PWM_CMPDAT1 cleared.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN2 : PWM-Timer 2 Enable/Disable Start Run
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PINV2 : PWM-Timer 2 Output Inverter Enabled/Disabled
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTMODE2 : PWM-Timer 2 Auto-Reload/One-Shot Mode\nNote: If there is a rising transition at this bit, it will cause PWM_PERIOD2 and PWM_CMPDAT2 cleared.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN3 : PWM-Timer 3 Enable/Disable Start Run
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PINV3 : PWM-Timer 3 Output Inverter Enabled/Disabled
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTMODE3 : PWM-Timer 3 Auto-Reload/One-Shot Mode\nNote: If there is a rising transition at this bit, it will cause PWM_PERIOD3 and PWM_CMPDAT3 cleared.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN4 : PWM-Timer 4 Enable/Disable Start Run
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PINV4 : PWM-Timer 4 Output Inverter Enabled/Disabled
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTMODE4 : PWM-Timer 4 Auto-Reload/One-Shot Mode\nNote: If there is a rising transition at this bit, it will cause PWM_PERIOD4 and PWM_CMPDAT4 cleared.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN5 : PWM-Timer 5 Enable/Disable Start Run
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ASYMEN : Asymmetric Mode In Center-Aligned Type
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PINV5 : PWM-Timer 5 Output Inverter Enabled/Disabled
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTMODE5 : PWM-Timer 5 Auto-Reload/One-Shot Mode\nNote: If there is a rising transition at this bit, it will cause PWM_PERIOD5 and PWM_CMPDAT5 cleared.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DTCNT01 : Dead-Zone 0 Generator Enable/Disable (PWM0 And PWM1 Pair For PWM Group)\nNote: When the dead-zone generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DTCNT23 : Dead-Zone 2 Generator Enable/Disable (PWM2 And PWM3 Pair For PWM Group)\nNote: When the dead-zone generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DTCNT45 : Dead-Zone 4 Generator Enable/Disable (PWM4 And PWM5 Pair For PWM Group)\nNote: When the dead-zone generator is enabled, the pair of PWM4 and PWM5 becomes a complementary pair for PWM group.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTCLR : Clear PWM Counter Control Bit\nNote: It is automatically cleared by hardware.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE : PWM Operating Mode Selection
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GROUPEN : Group Bit
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTTYPE : PWM Aligned Type Selection Bit
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MASKEND6 : MASK For D6
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MASKEND7 : MASK For D7
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POSCTL0 : ACMP0 Positive Input Selection Control Note: Register CMP0CR is describe in Comparator Controller chapter
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POSCTL1 : ACMP1 Positive Input Selection Control\nNote: Register CMP1CR is describe in Comparator Controller chapter
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IFAEN : Interrupt Accumulation Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IFCNT : Interrupt Accumulation Count\nWhen IFCNT is set, IFCNT will decrease when every ZIF0 flag is set and when IFCNT reach to zero, the PWM0 interrupt will occurred and IFCNT will reload itself.
bits : 4 - 7 (4 bit)
access : read-write

PERIOD : PWM Counter/Timer Loaded Value\nPERIOD determines the PWM period.\nEdge-aligned mode:\nNote: Any write to PERIOD will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write