UART_DAT

UART_MODEM

UART_MODEMSTS

UART_FIFOSTS

UART_INTSTS

UART_TOUT

UART_BAUD

UART_IRDA

UART_ALTCTL

UART_FUNCSEL

UART_INTEN

UART_FIFO

UART_LINE

DAT : Receiving/Transmit Buffer\nWrite Operation:\nBy writing to this register, the UART sends out an 8-bit data through the TX pin (LSB first). \nBy reading this register, the UART Controller will return an 8-bit data received from RX pin (LSB first).
bits : 0 - 7 (8 bit)
access : read-write

RTS : RTS (Request-To-Send) Signal Control\nThis bit is direct control internal RTS signal active or not, and then drive the RTS pin output with RTSACTLV bit configuration.\nNote1: This RTS signal control bit is not effective when RTS auto-flow control is enabled in UART function mode.\nNote2: This RTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTSACTLV : RTS Pin Active Level\nThis bit defines the active level state of RTS pin output.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTSSTS : RTS Pin State (Read Only)\nThis bit mirror from RTS pin output of voltage logic status.
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CTSDETF : Detect CTS State Change Flag\nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CTSSTS : CTS Pin Status (Read Only)\nThis bit mirror from CTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled, and CTS multi-function port is selected.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CTSACTLV : CTS Pin Active Level\nThis bit defines the active level state of CTS pin input.\nNote: Refer to Figure 6.1410
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXOVIF : RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, 16 bytes this bit will be set.\nNote: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADDRDETF : RS-485 Address Byte Detection Flag \nNote1: This field is used for RS-485 function mode.\nNote2: This bit is cleared by writing 1 to it.
bits : 3 - 3 (1 bit)
access : read-write

PEF : Parity Error Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid parity bit .
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

FEF : Framing Error Flag (Read Only)\nNote: This bit is read only, but can be cleared by writing '1' to it .
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BIF : Break Interrupt Flag (Read Only) This bit is set to logic 1 whenever the received data input (RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). Note: This bit is read only, but software can write 1 to clear it.
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXPTR : RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15.
bits : 8 - 13 (6 bit)
access : read-only

RXEMPTY : Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXFULL : Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise is cleared by hardware..
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXPTR : TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15.
bits : 16 - 21 (6 bit)
access : read-only

TXEMPTY : Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into DAT (TX FIFO not empty).
bits : 22 - 22 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXFULL : Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
bits : 23 - 23 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXOVIF : TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit is cleared by writing 1 to it.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXEMPTYF : Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RDAIF : Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL).
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

THREIF : Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN [1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into DAT (TX FIFO not empty).
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RLSIF : Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: This bit is read only and reset to 0 when all bits of BIF, FEF, PEF and ADDRDETF are cleared.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

MODENIF : MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF.
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXTOIF : Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If RXTOIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BUFERRIF : Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX/RX FIFO overflow flag (TXOVIF or RXOVIF) is set. \nWhen BUFERRIF is set, the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of TXOVIF and RXOVIF are cleared.
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RDAINT : Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN and RDAIF are both set to 1.\nThis bit is set if RDAIEN and RDAIF are both set to 1.
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

THREINT : Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN and THREIF are both set to 1.
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RLSINT : Receive Line Status Interrupt (Read Only)\nThis bit is set if RLSIEN and RLSIF are both set to 1.
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

MODEMINT : MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN and MODENIF are both set to 1.
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXTOINT : Time-Out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN and RXTOIF are both set to 1.
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BUFERRINT : Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN and BUFERRIF are both set to 1.
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TOIC : Time-Out Interrupt Comparator
bits : 0 - 7 (8 bit)
access : read-write

DLY : TX Delay Time Value\nThis field is used to program the transfer delay time between the last stop bit and next start bit.
bits : 8 - 15 (8 bit)
access : read-write

BRD : Baud Rate Divider\nThe field indicates the baud rate divider.
bits : 0 - 15 (16 bit)
access : read-write

EDIVM1 : Divider X
bits : 24 - 27 (4 bit)
access : read-write

BAUDM0 : Divider X Equal 1 UART Controller Baud Rate Generator Refer to section UART Controller Baud Rate Generator for more information.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BAUDM1 : Divider X Enable\nRefer to the table below for more information.\nNote: When in IrDA mode, this bit must be disabled.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXEN : TXEN
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXINV : TXINV
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXINV : RXINV
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS485NMM : RS-485 Normal Multi-Drop Operation Mode (NMM) Control\nNote: It cannot be active with RS485AAD operation mode.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS485AAD : RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS485NMM operation mode.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS485AUD : RS-485 Auto Direction Mode (AUD) Control\nNote: It can be active with RS485ADD or RS485NMM operation mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADDRDEN : RS-485 Address Detection Enable Control\nThis bit is used to enable RS-485 Address Detection mode.\nNote: This field is used for RS-485 any operation mode.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADDRMV : Address Match Value Register\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
bits : 24 - 31 (8 bit)
access : read-write

FUNCSEL : Function Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RDAIEN : Receive Data Available Interrupt Enable Control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

THREIEN : Transmit Holding Register Empty Interrupt Enable Control
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RLSIEN : Receive Line Status Interrupt Enable Control
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODEMIEN : Modem Status Interrupt Enable Control
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXTOIEN : RX Time-Out Interrupt Enable Control
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUFERRIEN : Buffer Error Interrupt Enable Control
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKCTSIEN : Wake-Up CPU Function Enable Control Note: when the chip is in Power-down mode, an external CTS change will wake-up chip from Power-down mode.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TOCNTEN : Time-Out Counter Enable Control
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ATORTSEN : RTS Auto Flow Control Enable Control\nNote: When RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO [19:16]), the UART will de-assert RTS signal.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ATOCTSEN : CTS Auto Flow Control Enable Control\nNote: When CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted).
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXRST : RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART Controller peripheral clock cycles.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXRST : TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART Controller peripheral clock cycles.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RFITL : RX FIFO Interrupt (RDAINT) Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL then the RDAIF will be set (if RDAIEN in UART_INTEN register is enable, an interrupt will generated).
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXOFF : Receiver Disable Register\nThe receiver is disabled or not (setting 1 to disable the receiver).\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485_NMM (UART_ALTCTL [8]) is programmed.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTSTRGLV : RTS Trigger Level (for Auto-flow Control Use)\nNote: This field is used for RTS auto-flow control.
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WLS : Word Length Selection
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NSB : Number Of STOP Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PBE : Parity Bit Enable Control
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EPE : Even Parity Enable Control\nThis bit has effect only when PBE (UART_LINE[3]) is set.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPE : Stick Parity Enable Control
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BCB : Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.