SYS_PDID (PDID)

SYS_REGLCTL (REGLCTL)

SYS_BODCTL (BODCTL)

SYS_P0_MFP (P0_MFP)

SYS_P1_MFP (P1_MFP)

SYS_P2_MFP (P2_MFP)

SYS_P3_MFP (P3_MFP)

SYS_RSTSTS (RSTSTS)

SYS_P4_MFP (P4_MFP)

SYS_P5_MFP (P5_MFP)

SYS_IPRST0 (IPRST0)

SYS_IRCTCTL (IRCTCTL)

SYS_IRCTIEN (IRCTIEN)

SYS_IRCTISTS (IRCTISTS)

SYS_IPRST1 (IPRST1)

PDID : Product Device Identification Number (Read Only) This register reflects the device part number code. Software can read this register to identify which device is used. For example, the MINI58LDE PDID code is 0x00A05800 .
bits : 0 - 31 (32 bit)
access : read-only

REGLCTL : Register Write-protection Code Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 0x59, 0x16, 0x88 to this field. After this sequence is completed, the REGLCTL bit 0 will be set to 1 and write-protection registers can be normal write. Register Write-protection Disable Index Please refer to 6.2.6 Register Protection.Note: The bits which are write-protected will be noted as (Write Protect) beside the description.
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODEN : Brown-out Detector Selection Extension (Initiated Write-protected Bit)
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODVL : Brown-out Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by flash controller user configuration register CBOV (CONFIG0[22:21]).\n
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODRSTEN : Brown-out Reset Enable Bit (Write Protect)\nThe default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit.\nNote: When the BOD_EN is enabled and the interrupt is asserted, the interrupt will be kept till the BOD_EN is set to 0. The interrupt for CPU can be blocked by disabling the NVIC in CPU for BOD interrupt or disable the interrupt source by disabling the BOD_EN and then re-enabling the BOD_EN function if the BOD function is required.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODIF : Brown-out Detector Interrupt Flag\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODLPM : Brown-out Detector Low Power Mode (Write Protect)\nNote: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODOUT : Brown-out Detector Output Status\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFP : P0 Multiple Function Select Bit\nThe pin function of P0 depends on MFP and ALT.\nRefer to ALT Description for details.
bits : 0 - 7 (8 bit)
access : read-write

ALT0 : P0.0 Alternate Function Select Bit\nBits ALT[0] (SYS_P0_MFP[8]), and MFP[0] (SYS_P0_MFP[0]) determine the P0.0 function.\n
bits : 8 - 8 (1 bit)
access : read-write

ALT1 : P0.1 Alternate Function Select Bit\nBits ALT[1] (SYS_P0_MFP[9]), and MFP[1] (SYS_P0_MFP[1]) determine the P0.1 function.\n
bits : 9 - 9 (1 bit)
access : read-write

ALT4 : P0.4 Alternate Function Select Bit\nBits ALT[4] (SYS_P0_MFP[12]), and MFP[4] (SYS_P0_MFP[4]) determine the P0.4 function.\n
bits : 12 - 12 (1 bit)
access : read-write

ALT5 : P0.5 Alternate Function Select Bit\nBits ALT[5] (SYS_P0_MFP[13]), and MFP[5] (SYS_P0_MFP[5]) determine the P0.5 function.\n
bits : 13 - 13 (1 bit)
access : read-write

ALT6 : P0.6 Alternate Function Select Bit\nBits ALT[6] (SYS_P0_MFP[14]), and MFP[6] (SYS_P0_MFP[6]) determine the P0.6 function.\n
bits : 14 - 14 (1 bit)
access : read-write

ALT7 : P0.7 Alternate Function Select Bit\nBits ALT[7] (SYS_P0_MFP[15]), and MFP[7] (SYS_P0_MFP[7]) determine the P0.7 function.\n
bits : 15 - 15 (1 bit)
access : read-write

TYPE : P0[7:0] Input Schmitt Trigger Function Enable Bits\n
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFP : P1 Multiple Function Select Bit\nThe pin function of P1 depends on MFP and ALT.\nRefer to ALT Description for details.
bits : 0 - 7 (8 bit)
access : read-write

ALT0 : P1.0 Alternate Function Select Bit\nBits ALT[0] (SYS_P1_MFP[8]), and MFP[0] (SYS_P1_MFP[0]) determine the P1.0 function.\n
bits : 8 - 8 (1 bit)
access : read-write

ALT2 : P1.2 Alternate Function Select Bit\nBits P12EXT (SYS_P1_MFP[26]), ALT[2] (SYS_P1_MFP[10]), and MFP[2] (SYS_P1_MFP[2]) determine the P1.2 function.\n
bits : 10 - 10 (1 bit)
access : read-write

ALT3 : P1.3 Alternate Function Select Bit\nBits P13EXT (SYS_P1_MFP[27]), ALT[3] (SYS_P1_MFP[11]), and MFP[3] (SYS_P1_MFP[3]) determine the P1.3 function.\n
bits : 11 - 11 (1 bit)
access : read-write

ALT4 : P1.4 Alternate Function Select Bit\nBits P14EXT (SYS_P1_MFP[28]), ALT[4] (SYS_P1_MFP[12]), and MFP[4] (SYS_P1_MFP[4]) determine the P1.4 function.\n
bits : 12 - 12 (1 bit)
access : read-write

ALT5 : P1.5 Alternate Function Select Bit\nBits ALT[5] (SYS_P1_MFP[13]), and MFP[5] (SYS_P1_MFP[5]) determine the P1.5 function.\n
bits : 13 - 13 (1 bit)
access : read-write

TYPE : P1[7:0] Input Schmitt Trigger Function Enable Bit\n
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

P12EXT : P1.2 Alternate Function Selection Extension\nBits P12EXT (SYS_P1_MFP[26]), ALT[2] (SYS_P1_MFP[10]), and MFP[2] (SYS_P1_MFP[2]) determine the P1.2 function.\n
bits : 26 - 26 (1 bit)
access : read-write

P13EXT : P1.3 Alternate Function Selection Extension\nBits P13EXT (SYS_P1_MFP[27]), ALT[3] (SYS_P1_MFP[11]), and MFP[3] (SYS_P1_MFP[3]) determine the P1.3 function.\n
bits : 27 - 27 (1 bit)
access : read-write

P14EXT : P1.4 Alternate Function Selection Extension\nBits P14EXT (SYS_P1_MFP[28]), ALT[4] (SYS_P1_MFP[12]), and MFP[4] (SYS_P1_MFP[4]) determine the P1.4 function.\n
bits : 28 - 28 (1 bit)
access : read-write

MFP : P2 Multiple Function Select Bit\nThe pin function of P2 depends on MFP and ALT.\nRefer to ALT Description for details.
bits : 0 - 7 (8 bit)
access : read-write

ALT2 : P2.2 Alternate Function Select Bit\nBits ALT[2] (SYS_P2_MFP[10]), and MFP[2] (SYS_P2_MFP[2]) determine the P2.2 function.\n
bits : 10 - 10 (1 bit)
access : read-write

ALT3 : P2.3 Alternate Function Select Bit\nBits ALT[3] (SYS_P2_MFP[11]), and MFP[3] (SYS_P2_MFP[3]) determine the P2.3 function.\n
bits : 11 - 11 (1 bit)
access : read-write

ALT4 : P2.4 Alternate Function Select Bit\nBits ALT[4] (SYS_P2_MFP[12]), and MFP[4] (SYS_P2_MFP[4]) determine the P2.4 function.\n
bits : 12 - 12 (1 bit)
access : read-write

ALT5 : P2.5 Alternate Function Select Bit\nBits ALT[5] (SYS_P2_MFP[13]), and MFP[5] (SYS_P2_MFP[5]) determine the P2.5 function.\n
bits : 13 - 13 (1 bit)
access : read-write

ALT6 : P2.6 Alternate Function Select Bit\nBits ALT[6] (SYS_P2_MFP[14]), and MFP[6] (SYS_P2_MFP[6]) determine the P2.6 function.\n
bits : 14 - 14 (1 bit)
access : read-write

TYPE : P2[7:0] Input Schmitt Trigger Function Enable Bits\n
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFP : P3 Multiple Function Select Bits\nThe pin function of P3 depends on MFP and ALT.\nRefer to ALT Description for details.
bits : 0 - 7 (8 bit)
access : read-write

ALT0 : P3.0 Alternate Function Select Bit\nBits ALT[0] (SYS_P3_MFP[8]), and MFP[0] (SYS_P3_MFP[0]) determine the P3.0 function.\n
bits : 8 - 8 (1 bit)
access : read-write

ALT1 : P3.1 Alternate Function Select Bit\nThe pin function of P3.1 depends on P3_MFP[1] and P3_ALT[1].\nBits ALT[1] (SYS_P3_MFP[9]), and MFP[1] (SYS_P3_MFP[1]) determine the P3.1 function.\n
bits : 9 - 9 (1 bit)
access : read-write

ALT2 : P3.2 Alternate Function Select Bit\nBits P32EXT (SYS_P3_MFP[26]), ALT[2] (SYS_P3_MFP[10]), and MFP[2] (SYS_P3_MFP[2]) determine the P3.2 function.\n
bits : 10 - 10 (1 bit)
access : read-write

ALT4 : P3.4 Alternate Function Select Bit\nBits ALT[4] (SYS_P3_MFP[12]), and MFP[4] (SYS_P3_MFP[4]) determine the P3.4 function.\n
bits : 12 - 12 (1 bit)
access : read-write

ALT5 : P3.5 Alternate Function Select Bit\nBits ALT[5] (SYS_P3_MFP[13]), and MFP[5] (SYS_P3_MFP[5]) determine the P3.5 function.\n
bits : 13 - 13 (1 bit)
access : read-write

ALT6 : P3.6 Alternate Function Select Bit\nBits ALT[6] (SYS_P3_MFP[14]), and MFP[6] (SYS_P3_MFP[6]) determine the P3.6 function.\n
bits : 14 - 14 (1 bit)
access : read-write

TYPE : P3[7:0] Input Schmitt Trigger Function Enable Bits\n
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

P32EXT : P3.2 Alternate Function Selection Extension\nBits P32EXT (SYS_P3_MFP[26]), ALT[2] (SYS_P3_MFP[10]), and MFP[2] (SYS_P3_MFP[2]) determine the P3.2 function.\n
bits : 26 - 26 (1 bit)
access : read-write

PORF : POR Reset Flag The POR reset flag is set by the Reset Signal from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source. Note: Software can write 1 to clear this bit to zero.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PINRF : NRESET Pin Reset Flag The nRESET pin reset flag is set by the Reset Signal from the nRESET pin to indicate the previous reset source. Note: Software can write 1 to clear this bit to zero.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDTRF : WDT Reset Flag The WDT reset flag is set by the Reset Signal from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source. Note: Software can write 1 to clear this bit to zero.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODRF : BOD Reset Flag The BOD reset flag is set by the Reset Signal from the Brown-out Detector to indicate the previous reset source. Note: Software can write 1 to clear this bit to zero.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYSRF : System Reset Flag The system reset flag is set by the Reset Signal from the Cortex-M0 Core to indicate the previous reset source. Note: Software can write 1 to clear this bit to zero.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPURF : CPU Reset Flag\nThe CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M0 Core and Flash Memory Controller (FMC).\nNote: Software can write 1 to clear this bit to zero.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPULKRF : The Cortex-M0 LOCKUP Flag\nNote: Software can write 1 to clear this bit to zero.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFP : P4 Multiple Function Select Bits\nThe pin function of P4 depends on MFP and ALT.\nRefer to ALT Description for details.
bits : 0 - 7 (8 bit)
access : read-write

ALT6 : P4.6 Alternate Function Select Bit\nBits ALT[6] (SYS_P4_MFP[14]), and MFP[6] (SYS_P4_MFP[6]) determine the P4.6 function.\n
bits : 14 - 14 (1 bit)
access : read-write

ALT7 : P4.7 Alternate Function Select Bit\nBits ALT[7] (SYS_P4_MFP[15]), and MFP[7] (SYS_P4_MFP[7]) determine the P4.7 function.\n
bits : 15 - 15 (1 bit)
access : read-write

TYPE : P4[7:0] Input Schmitt Trigger Function Enable Bits\n
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFP : P5 Multiple Function Select Bits\nThe pin function of P5 depends on MFP and ALT.\nRefer to ALT Description for details.
bits : 0 - 7 (8 bit)
access : read-write

ALT0 : P5.0 Alternate Function Select Bit\nThe pin function of P5.0 depends on MFP[0] and ALT[0].\nBits ALT[0] (SYS_P5_MFP[8]), and MFP[0] (SYS_P5_MFP[0]) determine the P5.0 function.\nNote: To enable external XTAL function, the CLK_PWRCTL bit [1:0] (XTLEN), external HXT or LXT crystal oscillator control register must also be set.
bits : 8 - 8 (1 bit)
access : read-write

ALT1 : P5.1 Alternate Function Select Bit\nBits ALT[1] (SYS_P5_MFP[9]), and MFP[1] (SYS_P5_MFP[1]) determine the P5.1 function.\nNote: To enable external XTAL function, the CLK_PWRCTL bit [1:0] (XTLEN), external HXT or LXT crystal oscillator control register must also be set.
bits : 9 - 9 (1 bit)
access : read-write

ALT2 : P5.2 Alternate Function Select Bit\nBits ALT[2] (SYS_P5_MFP[10]), and MFP[2] (SYS_P5_MFP[2]) determine the P5.2 function.\n
bits : 10 - 10 (1 bit)
access : read-write

ALT3 : P5.3 Alternate Function Select Bit\nBits ALT[3] (SYS_P5_MFP[11]), and MFP[3] (SYS_P5_MFP[3]) determine the P5.3 function.\n
bits : 11 - 11 (1 bit)
access : read-write

ALT4 : P5.4 Alternate Function Select Bit\nBits ALT[4] (SYS_P5_MFP[12]), and MFP[4] (SYS_P5_MFP[4]) determine the P5.4 function.\n
bits : 12 - 12 (1 bit)
access : read-write

ALT5 : P5.5 Alternate Function Select Bit\nBits ALT[5] (SYS_P5_MFP[13]), and MFP[5] (SYS_P5_MFP[5]) determine the P5.5 function.\n
bits : 13 - 13 (1 bit)
access : read-write

TYPE : P5[7:0] Input Schmitt Trigger Function Enable Bits\n
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHIPRST : CHIP One-shot Reset (Write Protect)\nSetting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is the same as the POR reset, all the chip controllers is reset and the chip settings from flash are also reload.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPURST : Processor Core One-shot Reset (Write Protect)\nSetting this bit will only reset the processor core and Flash Memory Controller (FMC), and this bit will automatically return to 0 after the 2 clock cycles.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FREQSEL : Trim Frequency Select Bit\nThis bit is to enable the HIRC auto trim.\nWhen setting this bit to 1, the HIRC auto trim function will trim HIRC to 22.1184 MHz automatically based on the LXT reference clock.\nDuring auto trim operation, if LXT clock error is detected or trim retry limitation count reached, this field will be cleared to 0 automatically.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LOOPSEL : Trim Calculation Loop This field defines trim value calculation based on the number of LXT clock. For example, if LOOPSEL is set as 00 , auto trim circuit will calculate trim value based on the average frequency difference in 4 LXT clocks. This field also defines how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC is locked. Once the HIRC is locked, the internal trim value update counter will be reset. If the trim value update counter reaches this limitation value and frequency of HIRC is still not locked, the auto trim operation will be disabled and FREQSEL will be cleared to 0.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TFAILIEN : Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count is reached and HIRC frequency is still not locked on target frequency set by FREQSEL (SYS_IRCTCTL[1:0]).\nIf this bit is high and TFAILIF (SYS_IRCTISTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count is reached.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKEIEN : LXT Clock Error Interrupt Enable Bit\nThis bit controls if CPU could get an interrupt while LXT clock is inaccurate during auto trim operation.\nIf this bit is high, and CLKERRIF (SYS_IRCTISTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the LXT clock frequency is inaccurate.\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FREQLOCK : HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency locked in 22.1184 MHz.\nThis is a read only status bit and doesn't trigger any interrupt.
bits : 0 - 0 (1 bit)
access : read-write

TFAILIF : Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and HIRC clock frequency still doesn't lock. Once this bit is set, the auto trim operation stopped and FREQSEL (SYS_IRCTCTL[1:0]) will be cleared to 0 by hardware automatically.\nIf this bit is set and TFAILIEN (SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Software can write 1 to clear this bit to 0.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKERRIF : LXT Clock Error Interrupt Status\nThis bit indicates that LXT clock frequency is inaccuracy. Once this bit is set, the auto trim operation stopped and FREQSEL (SYS_IRCTCTL[0]) will be cleared to 0 by hardware automatically.\nIf this bit is set and CLKEIEN (SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the LXT clock frequency is inaccuracy. Software can write 1 to clear this bit to 0.\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIORST : GPIO (P0~P5) Controller Reset\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0RST : Timer0 Controller Reset\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1RST : Timer1 Controller Reset\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C0RST : I2C0 Controller Reset\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C1RST : I2C1 Controller Reset\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI0RST : SPI0 Controller Reset\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART0RST : UART0 Controller Reset\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART1RST : UART1 Controller Reset\n
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM0RST : PWM0 Controller Reset\n
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACMPRST : ACMP Controller Reset\n
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCRST : ADC Controller Reset\n
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.