\n

INT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x88 byte (0x0)
mem_usage : registers
protection : not protected

Registers

IRQ0_SRC

IRQ4_SRC

IRQ5_SRC

IRQ6_SRC

IRQ7_SRC

IRQ8_SRC

IRQ9_SRC

IRQ10_SRC

IRQ11_SRC

IRQ12_SRC

IRQ13_SRC

IRQ14_SRC

IRQ15_SRC

IRQ1_SRC

IRQ16_SRC

IRQ17_SRC

IRQ18_SRC

IRQ19_SRC

IRQ20_SRC

IRQ21_SRC

IRQ22_SRC

IRQ23_SRC

IRQ24_SRC

IRQ25_SRC

IRQ26_SRC

IRQ27_SRC

IRQ28_SRC

IRQ29_SRC

IRQ30_SRC

IRQ31_SRC

IRQ2_SRC

NMI_CON

MCU_IRQ

IRQ3_SRC


IRQ0_SRC

IRQ0 (BOD) Interrupt Source Identity
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ0_SRC IRQ0_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BOD_INT

BOD_INT : IRQ0 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

IRQ0 source is not from BOD interrupt (BOD_INT)

#1 : 1

IRQ0 source is from BOD interrupt (BOD_INT)

End of enumeration elements list.


IRQ4_SRC

IRQ4 (GP0/1) Interrupt Source Identity
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ4_SRC IRQ4_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GP0_INT GP1_INT

GP0_INT : IRQ4 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

IRQ4 source is not from GP0 interrupt (GP0_INT)

#1 : 1

IRQ4 source is from GP0 interrupt (GP0_INT)

End of enumeration elements list.

GP1_INT : IRQ4 Source Identity\n
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

IRQ4 source is not from GP1 interrupt (GP1_INT)

#1 : 1

IRQ4 source is from GP1 interrupt (GP1_INT)

End of enumeration elements list.


IRQ5_SRC

IRQ5 (GP2/3/4) Interrupt Source Identity
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ5_SRC IRQ5_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GP2_INT GP3_INT GP4_INT

GP2_INT : IRQ5 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

IRQ5 source is not from GP2 interrupt (GP2_INT)

#1 : 1

IRQ5 source is from GP2 interrupt (GP2_INT)

End of enumeration elements list.

GP3_INT : IRQ5 Source Identity\n
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

IRQ5 source is not from GP3 interrupt (GP3_INT)

#1 : 1

IRQ5 source is from GP3 interrupt (GP3_INT)

End of enumeration elements list.

GP4_INT : IRQ5 Source Identity\n
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

IRQ5 source is not from GP4 interrupt (GP4_INT)

#1 : 1

IRQ5 source is from GP4 interrupt (GP4_INT)

End of enumeration elements list.


IRQ6_SRC

IRQ6 (PWM) Interrupt Source Identity
address_offset : 0x18 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ6_SRC IRQ6_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_INT

PWM_INT : IRQ6 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

IRQ6 source is not from PWM interrupt (PWM_INT)

#1 : 1

IRQ6 source is from PWM interrupt (PWM_INT)

End of enumeration elements list.


IRQ7_SRC

IRQ7 (BRAKE) Interrupt Source Identity
address_offset : 0x1C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ7_SRC IRQ7_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRAKE_INT

BRAKE_INT : IRQ7 Source Identity \n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

IRQ7 source is not from Brake interrupt (BRAKE_INT)

#1 : 1

IRQ7 source is from Brake interrupt (BRAKE_INT)

End of enumeration elements list.


IRQ8_SRC

IRQ8 (TMR0) Interrupt Source Identity
address_offset : 0x20 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ8_SRC IRQ8_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMR0_INT

TMR0_INT : IRQ8 Source Identity \n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

IRQ8 source is not from Timer0 interrupt (TMR0_INT)

#1 : 1

IRQ8 source is from Timer0 interrupt (TMR0_INT)

End of enumeration elements list.


IRQ9_SRC

IRQ9 (TMR1) Interrupt Source Identity
address_offset : 0x24 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ9_SRC IRQ9_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMR1_INT

TMR1_INT : IRQ9 Source Identity \n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

IRQ9 source is not from Timer1 interrupt (TMR1_INT)

#1 : 1

IRQ9 source is from Timer1 interrupt (TMR1_INT)

End of enumeration elements list.


IRQ10_SRC

Reserved
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ10_SRC IRQ10_SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IRQ11_SRC

Reserved
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ11_SRC IRQ11_SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IRQ12_SRC

IRQ12 (UART0) Interrupt Source Identity
address_offset : 0x30 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ12_SRC IRQ12_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART0_INT

UART0_INT : IRQ12 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

IRQ12 source is not from UART0 interrupt (UART0_INT)

#1 : 1

IRQ12 source is from UART0 interrupt (UART0_INT)

End of enumeration elements list.


IRQ13_SRC

IRQ13 (UART1) Interrupt Source Identity
address_offset : 0x34 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ13_SRC IRQ13_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART1_INT

UART1_INT : IRQ13 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

IRQ13 source is not from UART1 interrupt (UART1_INT)

#1 : 1

IRQ13 source is from UART1 interrupt (UART1_INT)

End of enumeration elements list.


IRQ14_SRC

IRQ14 (SPI) Interrupt Source Identity
address_offset : 0x38 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ14_SRC IRQ14_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI_INT

SPI_INT : IRQ14 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

IRQ14 source is not from SPI interrupt (SPI_INT)

#1 : 1

IRQ14 source is from SPI interrupt (SPI_INT)

End of enumeration elements list.


IRQ15_SRC

Reserved
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ15_SRC IRQ15_SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IRQ1_SRC

IRQ1 (WDT) Interrupt Source Identity
address_offset : 0x4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ1_SRC IRQ1_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_INT WWDT_INT

WDT_INT : IRQ1 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

IRQ1 source is not from watchdog interrupt (WDT _INT)

#1 : 1

IRQ1 source is from watchdog interrupt (WDT_INT)

End of enumeration elements list.

WWDT_INT : IRQ1 Source Identity\n
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

IRQ1 source is not from window watchdog interrupt (WWDT _INT)

#1 : 1

IRQ1 source is from window watchdog interrupt (WWDT_INT)

End of enumeration elements list.


IRQ16_SRC

IRQ16 (GP5) Interrupt Source Identity
address_offset : 0x40 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ16_SRC IRQ16_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GP5_INT

GP5_INT : IRQ16 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

IRQ16 source is not from GP5 interrupt (GP5_INT)

#1 : 1

IRQ16 source is from GP5 interrupt (GP5_INT)

End of enumeration elements list.


IRQ17_SRC

IRQ17 (HIRC Trim) Interrupt Source Identity
address_offset : 0x44 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ17_SRC IRQ17_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIRC_TRIM_INT

HIRC_TRIM_INT : IRQ17 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

IRQ17 source is not from HIRC trim interrupt (HIRC_TRIM_INT)

#1 : 1

IRQ17 source is from HIRC trim interrupt (HIRC_TRIM_INT)

End of enumeration elements list.


IRQ18_SRC

IRQ18 (I2C0) Interrupt Source Identity
address_offset : 0x48 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ18_SRC IRQ18_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C0_INT

I2C0_INT : IRQ18 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

IRQ18 source is not from I2C0 interrupt (I2C0_INT)

#1 : 1

IRQ18 source is from I2C0 interrupt (I2C0_INT)

End of enumeration elements list.


IRQ19_SRC

IRQ19 (I2C1) Interrupt Source Identity
address_offset : 0x4C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ19_SRC IRQ19_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C1_INT

I2C1_INT : IRQ19 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

IRQ19 source is not from I2C1 interrupt (I2C1_INT)

#1 : 1

IRQ19 source is from I2C1 interrupt (I2C1_INT)

End of enumeration elements list.


IRQ20_SRC

Reserved
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ20_SRC IRQ20_SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IRQ21_SRC

Reserved
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ21_SRC IRQ21_SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IRQ22_SRC

Reserved
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ22_SRC IRQ22_SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IRQ23_SRC

Reserved
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ23_SRC IRQ23_SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IRQ24_SRC

Reserved
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ24_SRC IRQ24_SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IRQ25_SRC

IRQ25 (ACMP) Interrupt Source Identity
address_offset : 0x64 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ25_SRC IRQ25_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACMP_INT

ACMP_INT : IRQ25 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

IRQ25 source is not from ACMP interrupt (ACMP_INT)

#1 : 1

IRQ25 source is from ACMP interrupt (ACMP_INT)

End of enumeration elements list.


IRQ26_SRC

Reserved
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ26_SRC IRQ26_SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IRQ27_SRC

Reserved
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ27_SRC IRQ27_SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IRQ28_SRC

IRQ28 (PWRWU) Interrupt Source Identity
address_offset : 0x70 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ28_SRC IRQ28_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWRWU_INT

PWRWU_INT : IRQ28 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

IRQ28 source is not from PWRWU interrupt (PWRWU_INT)

#1 : 1

IRQ28 source is from PWREU interrupt (PWRWU_INT)

End of enumeration elements list.


IRQ29_SRC

IRQ29 (ADC) Interrupt Source Identity
address_offset : 0x74 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ29_SRC IRQ29_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_INT

ADC_INT : IRQ29 Source Identity \n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

IRQ29 source is not from ADC interrupt (ADC_INT)

#1 : 1

IRQ29 source is from ADC interrupt (ADC_INT)

End of enumeration elements list.


IRQ30_SRC

Reserved
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ30_SRC IRQ30_SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IRQ31_SRC

Reserved
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ31_SRC IRQ31_SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IRQ2_SRC

IRQ2 (EINT0) Interrupt Source Identity
address_offset : 0x8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ2_SRC IRQ2_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EINT0

EINT0 : IRQ2 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

IRQ2 source is not from external signal interrupt 0 from P3.2 (EINT0)

#1 : 1

IRQ2 source is from external signal interrupt 0 from P3.2 (EINT0)

End of enumeration elements list.


NMI_CON

NMI Source Interrupt Select Control Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NMI_CON NMI_CON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NMI_SEL NMI_SEL_EN

NMI_SEL : NMI Interrupt Source Select Bit\nThe NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMI_SEL.
bits : 0 - 4 (5 bit)
access : read-write

NMI_SEL_EN : NMI Interrupt Enable Bit (Write Protected)\nNote: This bit is the protected bit, and programming it needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address SYS_BA+0x100.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

NMI interrupt Disabled

#1 : 1

NMI interrupt Enabled

End of enumeration elements list.


MCU_IRQ

MCU IRQ Number Identity Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCU_IRQ MCU_IRQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_IRQ

MCU_IRQ : MCU IRQ Source Bits\nThe MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0 core. There are two modes to generate interrupt to Cortex-M0 - the normal mode and test mode.\nThe MCU_IRQ collects all interrupts from each peripheral and synchronizes them then interrupts the Cortex-M0.\nWhen the MCU_IRQ[n] is 0, setting MCU_IRQ[n] to 1 will generate an interrupt to Cortex-M0 NVIC[n].\nWhen the MCU_IRQ[n] is 1 (mean an interrupt is assert), setting 1 to the MCU_bit[n] will clear the interrupt and setting MCU_IRQ[n] 0 has no effect.
bits : 0 - 31 (32 bit)
access : read-write


IRQ3_SRC

IRQ3 (EINT1) Interrupt Source Identity
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ3_SRC IRQ3_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EINT1

EINT1 : IRQ3 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

IRQ3 source is not from external signal interrupt 1 from P5.2 (EINT1)

#1 : 1

IRQ3 source is from external signal interrupt 1 from P5.2 (EINT1)

End of enumeration elements list.



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.