Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x200 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x180 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x40 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x80 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x140 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x210 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x228 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x248 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x260 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x270 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x298 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
P0 I/O Mode Control
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE0 : Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE1 : Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE2 : Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE3 : Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE4 : Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE5 : Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE6 : Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE7 : Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
P0 Pin Value
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PIN0 : Port 0-5 Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
bits : 0 - 0 (1 bit)
access : read-only
PIN1 : Port 0-5 Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
bits : 1 - 1 (1 bit)
access : read-only
PIN2 : Port 0-5 Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
bits : 2 - 2 (1 bit)
access : read-only
PIN3 : Port 0-5 Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
bits : 3 - 3 (1 bit)
access : read-only
PIN4 : Port 0-5 Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
bits : 4 - 4 (1 bit)
access : read-only
PIN5 : Port 0-5 Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
bits : 5 - 5 (1 bit)
access : read-only
PIN6 : Port 0-5 Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
bits : 6 - 6 (1 bit)
access : read-only
PIN7 : Port 0-5 Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
bits : 7 - 7 (1 bit)
access : read-only
P4 I/O Mode Control
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P4 Digital Input Path Disable Control
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P4 Data Output Value
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P4 Data Output Write Mask
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P4 Pin Value
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P4 De-bounce Enable Control
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P4 Interrupt Mode Control
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P4 Interrupt Enable Control
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P4 Interrupt Source Flag
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P0 De-bounce Enable Control
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBEN0 : Port 0-5 Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN1 : Port 0-5 Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN2 : Port 0-5 Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN3 : Port 0-5 Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN4 : Port 0-5 Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN5 : Port 0-5 Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN6 : Port 0-5 Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN7 : Port 0-5 Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
P5 I/O Mode Control
address_offset : 0x140 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P5 Digital Input Path Disable Control
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P5 Data Output Value
address_offset : 0x148 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P5 Data Output Write Mask
address_offset : 0x14C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P5 Pin Value
address_offset : 0x150 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P5 De-bounce Enable Control
address_offset : 0x154 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P5 Interrupt Mode Control
address_offset : 0x158 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P5 Interrupt Enable Control
address_offset : 0x15C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P5 Interrupt Source Flag
address_offset : 0x160 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P0 Interrupt Mode Control
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TYPE0 : Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE1 : Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE2 : Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE3 : Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE4 : Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE5 : Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE6 : Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE7 : Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
De-bounce Cycle Control
address_offset : 0x180 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBCLKSEL : De-bounce Sampling Cycle Selection\n
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
Sample interrupt input once per 1 clock
#0001 : 1
Sample interrupt input once per 2 clocks
#0010 : 2
Sample interrupt input once per 4 clocks
#0011 : 3
Sample interrupt input once per 8 clocks
#0100 : 4
Sample interrupt input once per 16 clocks
#0101 : 5
Sample interrupt input once per 32 clocks
#0110 : 6
Sample interrupt input once per 64 clocks
#0111 : 7
Sample interrupt input once per 128 clocks
#1000 : 8
Sample interrupt input once per 256 clocks
#1001 : 9
Sample interrupt input once per 2*256 clocks
#1010 : 10
Sample interrupt input once per 4*256 clocks
#1011 : 11
Sample interrupt input once per 8*256 clocks
#1100 : 12
Sample interrupt input once per 16*256 clocks
#1101 : 13
Sample interrupt input once per 32*256 clocks
#1110 : 14
Sample interrupt input once per 64*256 clocks
#1111 : 15
Sample interrupt input once per 128*256 clocks
End of enumeration elements list.
DBCLKSRC : De-bounce Counter Clock Source Selection\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
De-bounce counter clock source is HCLK
#1 : 1
De-bounce counter clock source is 10 kHz internal low speed RC oscillator (LIRC)
End of enumeration elements list.
ICLKON : Interrupt Clock On Mode\nNote: It is recommended to disable this bit to save system power if no special application concern.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1
#1 : 1
All I/O pins edge detection circuit is always active after reset
End of enumeration elements list.
P0 Interrupt Enable Control
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLIEN0 : Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN1 : Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN2 : Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN3 : Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN4 : Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN5 : Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN6 : Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN7 : Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
RHIEN0 : Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN1 : Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN2 : Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN3 : Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN4 : Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN5 : Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN6 : Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN7 : Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
P0 Interrupt Source Flag
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTSRC0 : Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.\nNo interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
End of enumeration elements list.
INTSRC1 : Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.\nNo interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
End of enumeration elements list.
INTSRC2 : Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.\nNo interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
End of enumeration elements list.
INTSRC3 : Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.\nNo interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
End of enumeration elements list.
INTSRC4 : Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.\nNo interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
End of enumeration elements list.
INTSRC5 : Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.\nNo interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
End of enumeration elements list.
INTSRC6 : Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.\nNo interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
End of enumeration elements list.
INTSRC7 : Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.\nNo interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
End of enumeration elements list.
INTSRC8 : Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.\nNo interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
End of enumeration elements list.
INTSRC9 : Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.\nNo interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
End of enumeration elements list.
INTSRC10 : Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.\nNo interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
End of enumeration elements list.
INTSRC11 : Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.\nNo interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
End of enumeration elements list.
INTSRC12 : Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.\nNo interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
End of enumeration elements list.
INTSRC13 : Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.\nNo interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
End of enumeration elements list.
INTSRC14 : Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.\nNo interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
End of enumeration elements list.
INTSRC15 : Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.\nNo interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
End of enumeration elements list.
GPIO P0.0 Pin Data Input/Output
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDIO : GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding GPIO pin set to low
#1 : 1
Corresponding GPIO pin set to high
End of enumeration elements list.
GPIO P0.1 Pin Data Input/Output
address_offset : 0x204 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P0.4 Pin Data Input/Output
address_offset : 0x210 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P0.5 Pin Data Input/Output
address_offset : 0x214 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P0.6 Pin Data Input/Output
address_offset : 0x218 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P0.7 Pin Data Input/Output
address_offset : 0x21C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P1.0 Pin Data Input/Output
address_offset : 0x220 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P1.2 Pin Data Input/Output
address_offset : 0x228 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P1.3 Pin Data Input/Output
address_offset : 0x22C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P1.4 Pin Data Input/Output
address_offset : 0x230 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P1.5 Pin Data Input/Output
address_offset : 0x234 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P2.2 Pin Data Input/Output
address_offset : 0x248 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P2.3 Pin Data Input/Output
address_offset : 0x24C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P2.4 Pin Data Input/Output
address_offset : 0x250 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P2.5 Pin Data Input/Output
address_offset : 0x254 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P2.6 Pin Data Input/Output
address_offset : 0x258 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P3.0 Pin Data Input/Output
address_offset : 0x260 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P3.1 Pin Data Input/Output
address_offset : 0x264 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P3.2 Pin Data Input/Output
address_offset : 0x268 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P3.4 Pin Data Input/Output
address_offset : 0x270 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P3.5 Pin Data Input/Output
address_offset : 0x274 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P3.6 Pin Data Input/Output
address_offset : 0x278 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P4.6 Pin Data Input/Output
address_offset : 0x298 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P4.7 Pin Data Input/Output
address_offset : 0x29C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P5.0 Pin Data Input/Output
address_offset : 0x2A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P5.1 Pin Data Input/Output
address_offset : 0x2A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P5.2 Pin Data Input/Output
address_offset : 0x2A8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P5.3 Pin Data Input/Output
address_offset : 0x2AC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P5.4 Pin Data Input/Output
address_offset : 0x2B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P5.5 Pin Data Input/Output
address_offset : 0x2B4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P0 Digital Input Path Disable Control
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DINOFF0 : Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF1 : Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF2 : Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\n
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF3 : Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\n
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF4 : Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\n
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF5 : Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\n
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF6 : Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\n
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF7 : Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\n
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
P1 I/O Mode Control
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1 Digital Input Path Disable Control
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1 Data Output Value
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1 Data Output Write Mask
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1 Pin Value
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1 De-bounce Enable Control
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1 Interrupt Mode Control
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1 Interrupt Enable Control
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1 Interrupt Source Flag
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P0 Data Output Value
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOUT0 : Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT1 : Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT2 : Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT3 : Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT4 : Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT5 : Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT6 : Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT7 : Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
P2 I/O Mode Control
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P2 Digital Input Path Disable Control
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P2 Data Output Value
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P2 Data Output Write Mask
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P2 Pin Value
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P2 De-bounce Enable Control
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P2 Interrupt Mode Control
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P2 Interrupt Enable Control
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P2 Interrupt Source Flag
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P0 Data Output Write Mask
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATMSK0 : Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK1 : Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK2 : Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK3 : Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK4 : Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK5 : Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK6 : Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK7 : Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
P3 I/O Mode Control
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P3 Digital Input Path Disable Control
address_offset : 0xC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P3 Data Output Value
address_offset : 0xC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P3 Data Output Write Mask
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P3 Pin Value
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P3 De-bounce Enable Control
address_offset : 0xD4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P3 Interrupt Mode Control
address_offset : 0xD8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P3 Interrupt Enable Control
address_offset : 0xDC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P3 Interrupt Source Flag
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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