PWM_CLKPSC

PWM_PERIOD1

PWM_PERIOD2

PWM_PERIOD3

PWM_PERIOD4

PWM_PERIOD5

PWM_CMPDAT0

PWM_CMPDAT1

PWM_CMPDAT2

PWM_CMPDAT3

PWM_CMPDAT4

PWM_CMPDAT5

PWM_CLKDIV

PWM_INTEN

PWM_INTSTS

PWM_POEN

PWM_BRKCTL

PWM_DTCTL

PWM_ADCTCTL0

PWM_ADCTCTL1

PWM_ADCTSTS0

PWM_ADCTSTS1

PWM_PHCHG

PWM_PHCHGNXT

PWM_CTL

PWM_PHCHGMSK

PWM_IFA

PWM_PCACTL

PWM_MSKALIGN

PWM_PERIOD0

CLKPSC01 : Clock Prescaler 0 For PWM Counter 0 And 1\nClock input is divided by (CLKPSC01 + 1) before it is fed to the corresponding PWM counter.\n
bits : 0 - 7 (8 bit)
access : read-write

CLKPSC23 : Clock Prescaler 2 For PWM Counter 2 And 3\nClock input is divided by (CLKPSC23 + 1) before it is fed to the corresponding PWM counter.\n
bits : 8 - 15 (8 bit)
access : read-write

CLKPSC45 : Clock Prescaler 4 For PWM Counter 4 And 5\nClock input is divided by (CLKPSC45 + 1) before it is fed to the corresponding PWM counter.\n
bits : 16 - 23 (8 bit)
access : read-write

CMPn : PWM Comparator Register\nCMP determines the PWM duty.\nEdge-aligned type:\nNote: Any write to CMPn will take effect in the next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write

CMPDn : PWM Comparator Register For Down Counter In Asymmetric Mode\nOthers: PWM output is always high.
bits : 16 - 31 (16 bit)
access : read-write

CLKDIV0 : Counter 0 Clock Divider Selection\nSelect clock input for PWM counter.\n
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKDIV1 : Counter 1 Clock Divider Selection\nSelect clock input for PWM counter.\n
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKDIV2 : Counter 2 Clock Divider Selection\nSelect clock input for PWM counter.\n
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKDIV3 : Counter 3 Clock Divider Selection\nSelect clock input for PWM counter.\n
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKDIV4 : Counter 4 Clock Divider Selection\nSelect clock input for PWM counter.\n
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKDIV5 : Counter 5 Clock Divider Selection\nSelect clock input for PWM counter.\n
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ZIEN0 : PWM Zero Point Interrupt Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ZIEN1 : PWM Zero Point Interrupt Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ZIEN2 : PWM Zero Point Interrupt Enable Bit\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ZIEN3 : PWM Zero Point Interrupt Enable Bit\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ZIEN4 : PWM Zero Point Interrupt Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ZIEN5 : PWM Zero Point Interrupt Enable Bit\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPDIEN0 : PWM Compare Down Interrupt Enable Bit\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPDIEN1 : PWM Compare Down Interrupt Enable Bit\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPDIEN2 : PWM Compare Down Interrupt Enable Bit\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPDIEN3 : PWM Compare Down Interrupt Enable Bit\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPDIEN4 : PWM Compare Down Interrupt Enable Bit\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPDIEN5 : PWM Compare Down Interrupt Enable Bit\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRKIEN : Fault Brake0 And Fault Brake1 Interrupt Enable Bit\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PINTTYPE : PWM Interrupt Type Selection\nNote: This bit is effective when PWM is in center-aligned type only.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PIEN0 : PWM Period Interrupt Enable Bit\n
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PIEN1 : PWM Period Interrupt Enable Bit\n
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PIEN2 : PWM Period Interrupt Enable Bit\n
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PIEN3 : PWM Period Interrupt Enable Bit\n
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PIEN4 : PWM Period Interrupt Enable Bit\n
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PIEN5 : PWM Period Interrupt Enable Bit\n
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPUIEN0 : PWM Compare Up Interrupt Enable Bit\n
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPUIEN1 : PWM Compare Up Interrupt Enable Bit\n
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPUIEN2 : PWM Compare Up Interrupt Enable Bit\n
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPUIEN3 : PWM Compare Up Interrupt Enable Bit\n
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPUIEN4 : PWM Compare Up Interrupt Enable Bit\n
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPUIEN5 : PWM Compare Up Interrupt Enable Bit\n
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ZIF0 : PWM Zero Point Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches zero point. \nNote: This bit can be cleared by software writing 1.
bits : 0 - 0 (1 bit)
access : read-write

ZIF1 : PWM Zero Point Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches zero point. \nNote: This bit can be cleared by software writing 1.
bits : 1 - 1 (1 bit)
access : read-write

ZIF2 : PWM Zero Point Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches zero point. \nNote: This bit can be cleared by software writing 1.
bits : 2 - 2 (1 bit)
access : read-write

ZIF3 : PWM Zero Point Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches zero point. \nNote: This bit can be cleared by software writing 1.
bits : 3 - 3 (1 bit)
access : read-write

ZIF4 : PWM Zero Point Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches zero point. \nNote: This bit can be cleared by software writing 1.
bits : 4 - 4 (1 bit)
access : read-write

ZIF5 : PWM Zero Point Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches zero point. \nNote: This bit can be cleared by software writing 1.
bits : 5 - 5 (1 bit)
access : read-write

CMPDIF0 : PWM Compare Down Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches CMPn. \nNote: This bit can be cleared by software writing 1.
bits : 8 - 8 (1 bit)
access : read-write

CMPDIF1 : PWM Compare Down Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches CMPn. \nNote: This bit can be cleared by software writing 1.
bits : 9 - 9 (1 bit)
access : read-write

CMPDIF2 : PWM Compare Down Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches CMPn. \nNote: This bit can be cleared by software writing 1.
bits : 10 - 10 (1 bit)
access : read-write

CMPDIF3 : PWM Compare Down Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches CMPn. \nNote: This bit can be cleared by software writing 1.
bits : 11 - 11 (1 bit)
access : read-write

CMPDIF4 : PWM Compare Down Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches CMPn. \nNote: This bit can be cleared by software writing 1.
bits : 12 - 12 (1 bit)
access : read-write

CMPDIF5 : PWM Compare Down Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches CMPn. \nNote: This bit can be cleared by software writing 1.
bits : 13 - 13 (1 bit)
access : read-write

BRKIF0 : PWM Brake0 Flag\nNote: This bit can be cleared by software writing 1.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRKIF1 : PWM Brake1 Flag\nNote: This bit can be cleared by software writing 1.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PIF0 : PWM Period Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter reaches PERIODn. \nNote: This bit can be cleared by software writing 1.
bits : 18 - 18 (1 bit)
access : read-write

PIF1 : PWM Period Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter reaches PERIODn. \nNote: This bit can be cleared by software writing 1.
bits : 19 - 19 (1 bit)
access : read-write

PIF2 : PWM Period Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter reaches PERIODn. \nNote: This bit can be cleared by software writing 1.
bits : 20 - 20 (1 bit)
access : read-write

PIF3 : PWM Period Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter reaches PERIODn. \nNote: This bit can be cleared by software writing 1.
bits : 21 - 21 (1 bit)
access : read-write

PIF4 : PWM Period Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter reaches PERIODn. \nNote: This bit can be cleared by software writing 1.
bits : 22 - 22 (1 bit)
access : read-write

PIF5 : PWM Period Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter reaches PERIODn. \nNote: This bit can be cleared by software writing 1.
bits : 23 - 23 (1 bit)
access : read-write

CMPUIF0 : PWM Compare Up Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter up count reaches CMPn. \nNote: This bit can be cleared by software writing 1.
bits : 24 - 24 (1 bit)
access : read-write

CMPUIF1 : PWM Compare Up Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter up count reaches CMPn. \nNote: This bit can be cleared by software writing 1.
bits : 25 - 25 (1 bit)
access : read-write

CMPUIF2 : PWM Compare Up Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter up count reaches CMPn. \nNote: This bit can be cleared by software writing 1.
bits : 26 - 26 (1 bit)
access : read-write

CMPUIF3 : PWM Compare Up Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter up count reaches CMPn. \nNote: This bit can be cleared by software writing 1.
bits : 27 - 27 (1 bit)
access : read-write

CMPUIF4 : PWM Compare Up Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter up count reaches CMPn. \nNote: This bit can be cleared by software writing 1.
bits : 28 - 28 (1 bit)
access : read-write

CMPUIF5 : PWM Compare Up Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter up count reaches CMPn. \nNote: This bit can be cleared by software writing 1.
bits : 29 - 29 (1 bit)
access : read-write

POEN0 : PWM Output Enable Bits\nNote: The corresponding GPIO pin must be switched to PWM function.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POEN1 : PWM Output Enable Bits\nNote: The corresponding GPIO pin must be switched to PWM function.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POEN2 : PWM Output Enable Bits\nNote: The corresponding GPIO pin must be switched to PWM function.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POEN3 : PWM Output Enable Bits\nNote: The corresponding GPIO pin must be switched to PWM function.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POEN4 : PWM Output Enable Bits\nNote: The corresponding GPIO pin must be switched to PWM function.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POEN5 : PWM Output Enable Bits\nNote: The corresponding GPIO pin must be switched to PWM function.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRK0EN : Enable BKP0 Pin Trigger Fault Brake Function 0\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRK1EN : Enable BKP1 Pin Trigger Fault Brake Function 1\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRK0SEL : BKP1 Fault Brake Function Source Select Bit\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRK1SEL : BKP0 Fault Brake Function Source Select Bit\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRKSTS : PWM Fault Brake Event Status Flag\nNote: This bit can be cleared by software writing 1 and must be cleared before restarting the PWM counter.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRKACT : PWM Brake Action Type\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SWBRK : Software Brake\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKOD0 : PWM Brake Output Data Select Bits\n
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKOD1 : PWM Brake Output Data Select Bits\n
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKOD2 : PWM Brake Output Data Select Bits\n
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKOD3 : PWM Brake Output Data Select Bits\n
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKOD4 : PWM Brake Output Data Select Bits\n
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKOD5 : PWM Brake Output Data Select Bits\n
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

D6BKOD : Channel 6 Brake Output Data Select Bit\n
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

D7BKOD : Channel 7 Brake Output Data Select Bit\n
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DTI01 : Dead-time Interval Register For Pair Of Channel0 And Channel1 (PWM0_CH0 And PWM0_CH1 Pair)\nThese 8 bits determine dead-time length.\nThe unit time of dead-time length is received from corresponding PWM_CLKDIV bits.
bits : 0 - 7 (8 bit)
access : read-write

DTI23 : Dead-time Interval Register For Pair Of Channel2 And Channel3 (PWM0_CH2 And PWM0_CH3 Pair)\nThese 8 bits determine dead-time length.\nThe unit time of dead-time length is received from corresponding PWM_CLKDIV bits.
bits : 8 - 15 (8 bit)
access : read-write

DTI45 : Dead-time Interval Register For Pair Of Channel4 And Channel5 (PWM0_CH4 And PWM0_CH5 Pair)\nThese 8 bits determine dead-time length.\nThe unit time of dead-time length is received from corresponding PWM_CLKDIV bits.
bits : 16 - 23 (8 bit)
access : read-write

CUTRGEN0 : Channel 0 Compare Up Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel0's counter matching CMP0 in up-count direction\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPTRGEN0 : Channel 0 Center Point Trigger ADC Enable Bit\nEnable PWM Trigger ADC Function While channel0's Counter Matching PERIOD0\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CDTRGEN0 : Channel 0 Compare Down Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel0's counter matching CMP0 in down-count direction\nNote: This bit is valid for both center-aligned type and edged-aligned type.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ZPTRGEN0 : Channel 0 Zero Point Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel0's counter matching 0\nNote: This bit is valid for both center-aligned type and edged-aligned type.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CUTRGEN1 : Channel 1 Compare Up Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel1's counter matching CMP1 in up-count direction\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPTRGEN1 : Channel 1 Center Point Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel1's counter matching PERIOD1\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CDTRGEN1 : Channel 1 Compare Down Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel1's counter matching CMP1 in down-count direction\nNote: This bit is valid for both center-aligned type and edged-aligned type.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ZPTRGEN1 : Channel 1 Zero Point Trigger ADC Enable Bit\nEnable PWM trigger ADC function While channel1's Counter Matching 0 \nNote: This bit is valid for both center-aligned type and edged-aligned type.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CUTRGEN2 : Channel 2 Compare Up Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel2's counter matching CMP2 in up-count direction\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPTRGEN2 : Channel 2 Center Point Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel2's counter matching PERIOD2\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CDTRGEN2 : Channel 2 Compare Down Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel2's counter matching CMP2 in down-count direction\nNote: This bit is valid for both center-aligned type and edged-aligned type.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ZPTRGEN2 : Channel 2 Zero Point Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel2's counter matching 0\nNote: This bit is valid for both center-aligned type and edged-aligned type.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CUTRGEN3 : Channel 3 Compare Up Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel3's counter matching CMP3 in up-count direction\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged aligned type, setting this bit is meaningless and will not take any effect.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPTRGEN3 : Channel 3 Center Point Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel3's counter matching PERIOD3\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged aligned type, setting this bit is meaningless and will not take any effect.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CDTRGEN3 : Channel 3 Compare Down Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel3's counter matching CMP3 in down-count direction\nNote: This bit is valid for both center-aligned type and edged aligned type.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ZPTRGEN3 : Channel 3 Zero Point Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel3's counter matching 0\nNote: This bit is valid for both center-aligned type and edged aligned type.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CUTRGEN4 : Channel 4 Compare Up Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel4's counter matching CMP4 in up-count direction\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPTRGEN4 : Channel 4 Center Point Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel4's counter matching PERIOD4\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CDTRGEN4 : Channel 4 Compare Down Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel4's counter matching CMP4 in down-count direction\nNote: This bit is valid for both center-aligned type and edged-aligned type.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ZPTRGEN4 : Channel 4 Zero Point Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel4's counter matching 0\nNote: This bit is valid for both center-aligned type and edged-aligned type.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CUTRGEN5 : Channel 5 Compare Up Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel5's counter matching CMP5 in up-count direction\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPTRGEN5 : Channel 5 Center Point Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel5's counter matching PERIOD5\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CDTRGEN5 : Channel 5 Compare Down Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel5's counter matching CMP5 in down-count direction\nNote: This bit is valid for both center-aligned type and edged-aligned type.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ZPTRGEN5 : Channel 5 Zero Point Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel5's counter matching 0\nNote: This bit is valid for both center-aligned type and edged-aligned type.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CUTRGF0 : Channel 0 Compare Up Trigger ADC Flag\nWhen the channel0's counter is counting up to CMP0, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
bits : 0 - 0 (1 bit)
access : read-write

CPTRGF0 : Channel 0 Center Point Trigger ADC Flag\nWhen the channel0's counter is counting to PERIOD0, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
bits : 1 - 1 (1 bit)
access : read-write

CDTRGF0 : Channel 0 Compare Down Trigger ADC Flag\nWhen the channel0's counter is counting down to CMP0, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
bits : 2 - 2 (1 bit)
access : read-write

ZPTRGF0 : Channel 0 Zero Point Trigger ADC Flag\nWhen the channel0's counter is counting to zero point, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
bits : 3 - 3 (1 bit)
access : read-write

CUTRGF1 : Channel 1 Compare Up Trigger ADC Flag\nWhen the channel1's counter is counting up to CMP1, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
bits : 8 - 8 (1 bit)
access : read-write

CPTRGF1 : Channel 1 Center Point Trigger ADC Flag\nWhen the channel1's counter is counting to PERIOD1, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
bits : 9 - 9 (1 bit)
access : read-write

CDTRGF1 : Channel 1 Compare Down Trigger ADC Flag\nWhen the channel1's counter is counting down to CMP1, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
bits : 10 - 10 (1 bit)
access : read-write

ZPTRGF1 : Channel 1 Zero Point Trigger ADC Flag\nWhen the channel1's counter is counting to zero point, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
bits : 11 - 11 (1 bit)
access : read-write

CUTRGF2 : Channel 2 Compare Up Trigger ADC Flag\nWhen the channel2's counter is counting up to CMP2, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
bits : 16 - 16 (1 bit)
access : read-write

CPTRGF2 : Channel 2 Center Point Trigger ADC Flag\nWhen the channel2's counter is counting to PERIOD2, this bit will be set for trigger ADC. Note: This bit can be cleared by software writing 1.
bits : 17 - 17 (1 bit)
access : read-write

CDTRGF2 : Channel 2 Compare Down Trigger ADC Flag\nWhen the channel2's counter is counting down to CMP2, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
bits : 18 - 18 (1 bit)
access : read-write

ZPTRGF2 : Channel 2 Zero Point Trigger ADC Enable Bit\nWhen the channel2's counter is counting to zero point, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
bits : 19 - 19 (1 bit)
access : read-write

CUTRGF3 : Channel 3 Compare Up Trigger ADC Flag\nWhen the channel3's counter is counting up to CMP3, this bit will be set for trigger ADC.\nNote: This bit can be cleared by software writing 1.
bits : 24 - 24 (1 bit)
access : read-write

CPTRGF3 : Channel 3 Center Point Trigger ADC Flag\nWhen the channel3's counter is counting to PERIOD3, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
bits : 25 - 25 (1 bit)
access : read-write

CDTRGF3 : Channel 3 Compare Down Trigger ADC Flag\nWhen the channel3's counter is counting down to CMP3, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
bits : 26 - 26 (1 bit)
access : read-write

ZPTRGF3 : Channel 3 Zero Point Trigger ADC Flag\nWhen the channel3's counter is counting to zero point, this bit will be set for trigger ADC.\nNote: This bit can be cleared by software writing 1.
bits : 27 - 27 (1 bit)
access : read-write

CUTRGF4 : Channel 4 Compare Up Trigger ADC Flag When the channel4's counter is counting up to CMP4, this bit will be set for trigger ADC. Note: This bit can be cleared by software writing 1.
bits : 0 - 0 (1 bit)
access : read-write

CPTRGF4 : Channel 4 Center Point Trigger ADC Flag\nWhen the channel4's counter is counting to PERIOD4, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
bits : 1 - 1 (1 bit)
access : read-write

CDTRGF4 : Channel 4 Compare Down Trigger ADC Flag\nWhen the channel4's counter is counting down to CMP4, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
bits : 2 - 2 (1 bit)
access : read-write

ZPTRGF4 : Channel 4 Zero Point Trigger ADC Flag\nWhen the channel4's counter is counting to zero point, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
bits : 3 - 3 (1 bit)
access : read-write

CUTRGF5 : Channel 5 Compare Up Trigger ADC Flag\nWhen the channel5's counter is counting up to CMP5, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
bits : 8 - 8 (1 bit)
access : read-write

CPTRGF5 : Channel 5 Center Point Trigger ADC Flag\nWhen the channel5's counter is counting to PERIOD5, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
bits : 9 - 9 (1 bit)
access : read-write

CDTRGF5 : Channel 5 Compare Down Trigger ADC Flag\nWhen the channel5's counter is counting down to CMP5, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
bits : 10 - 10 (1 bit)
access : read-write

ZPTRGF5 : Channel 5 Zero Point Trigger ADC Flag\nWhen the channel5's counter is counting to zero point, this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1.
bits : 11 - 11 (1 bit)
access : read-write

MSKDAT0 : PWM0_CHn Mask Data \nWhen MSKENn is 0, channel n's output level is MSKDATn.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT1 : PWM0_CHn Mask Data \nWhen MSKENn is 0, channel n's output level is MSKDATn.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT2 : PWM0_CHn Mask Data \nWhen MSKENn is 0, channel n's output level is MSKDATn.\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT3 : PWM0_CHn Mask Data \nWhen MSKENn is 0, channel n's output level is MSKDATn.\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT4 : PWM0_CHn Mask Data \nWhen MSKENn is 0, channel n's output level is MSKDATn.\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT5 : PWM0_CHn Mask Data \nWhen MSKENn is 0, channel n's output level is MSKDATn.\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT6 : PWM0_CH6 (GPIO P0.1) Mask Data \nWhen MASKEND6 Is 1, channel 6's output level is MSKDAT6.\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT7 : PWM0_CH7 (GPIO P0.0) Mask Data \nWhen MASKEND7 Is 1, channel 7's output level is MSKDAT7.\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKEN0 : PWMn Output Mask Enable Bits\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKEN1 : PWMn Output Mask Enable Bits\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKEN2 : PWMn Output Mask Enable Bits\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKEN3 : PWMn Output Mask Enable Bits\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKEN4 : PWMn Output Mask Enable Bits\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKEN5 : PWMn Output Mask Enable Bits\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AUTOCLR0 : Hardware Auto Clear ACMP0TEN\n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AUTOCLR1 : Hardware Auto Clear ACMP1TEN \n
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AOFFEN01 : ACMP1 Trigger Channel 0 One Cycle Output Off Enable Bit Setting this bit will force PWM channel 0 to output low lasting for at most one period cycle as long as ACMP1 trigger It This feature is usually in step motor application. Note: This function is only available for PWM0_CH0~PWM0_CH3.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AOFFEN11 : ACMP1 Trigger Channel 1 One Cycle Output Off Enable Bit Setting this bit will force PWM channel 1 to output low lasting for at most one period cycle as long as ACMP1 trigger It This feature is usually in step motor application. Note: This function is only available for PWM0_CH0~PWM0_CH3.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AOFFEN21 : ACMP1 Trigger Channel 2 One Cycle Output Off Enable Bit Setting this bit will force PWM channel 2 to output low lasting for at most one period cycle as long as ACMP1 trigger It This feature is usually in step motor application. Note: This function is only available for PWM0_CH0~PWM0_CH 3.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AOFFEN31 : ACMP1 Trigger Channel 3 One Cycle Output Off Enable Bit Setting this bit will force PWM channel 3 to output low lasting for at most one period cycle as long as ACMP1 trigger It This feature is usually in step motor application. Note: This function is only available for PWM0_CH0~PWM0_CH3.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

A1POSSEL : ACMP1 Positive Input Source Select Bits\n
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1TEN : TIMER1 Trigger PWM Function Enable Bit\nWhen this bit is set, TIMER1 time-out event will update PWM_PHCHG with PHCHG_NXT register.\n
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACMP1TEN : ACMP1 Trigger Function Enable Bit\nNote: This bit will be auto cleared when ACMP1 trigger PWM if AUTOCLR1 is set.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AOFFEN00 : ACMP0 Trigger Channel 0 One Cycle Output Off Enable Bit Setting this bit will force PWM channel 0 to output low lasting for at most one period cycle as long as ACMP0 trigger It This feature is usually in step motor application. Note: This function is only available for PWM0_CH0~PWM0_CH3.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AOFFEN10 : ACMP0 Trigger Channel 1 One Cycle Output Off Enable Bit Setting this bit will force PWM channel 1 to output low lasting for at most one period cycle as long as ACMP0 trigger It This feature is usually in step motor application. Note: This function is only available for PWM0_CH0~PWM0_CH3.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AOFFEN20 : ACMP0 Trigger Channel 2 One Cycle Output Off Enable Bit Setting this bit will force PWM channel 2 to output low lasting for at most one period cycle as long as ACMP0 trigger It This feature is usually in step motor application. Note: This function is only available for PWM0_CH0~PWM0_CH3.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AOFFEN30 : ACMP0 Trigger Channel 3 One Cycle Output Off Enable Bit Setting this bit will force PWM channel 3 to output low lasting for at most one period cycle as long as ACMP0 trigger It This feature is usually in step motor application. Note: This function is only available for PWM0_CH0~ PWM0_CH3.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

A0POSSEL : ACMP0 Positive Input Source Select Bits\n
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0TEN : TIMER0 Trigger PWM Function Enable Bit\nWhen this bit is set, TIMER0 time-out event will update PWM_PHCHG with PHCHG_NXT register.\n
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACMP0TEN : ACMP0 Trigger PWM Function Enable Bit\nNote: This bit will be auto cleared when ACMP0 trigger PWM if AUTOCLR0 is set.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT0 : PWM0_CHn Mask Data \nWhen MSKENn is 0, channel n's output level is MSKDATn.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT1 : PWM0_CHn Mask Data \nWhen MSKENn is 0, channel n's output level is MSKDATn.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT2 : PWM0_CHn Mask Data \nWhen MSKENn is 0, channel n's output level is MSKDATn.\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT3 : PWM0_CHn Mask Data \nWhen MSKENn is 0, channel n's output level is MSKDATn.\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT4 : PWM0_CHn Mask Data \nWhen MSKENn is 0, channel n's output level is MSKDATn.\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT5 : PWM0_CHn Mask Data \nWhen MSKENn is 0, channel n's output level is MSKDATn.\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT6 : PWM0_CH6 (GPIO P0.1) Mask Data \nWhen MASKEND6 Is 1, channel 6's output level is MSKDAT6.\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT7 : PWM0_CH7 (GPIO P0.0) Mask Data \nWhen MASKEND7 Is 1, channel 7's output level is MSKDAT7.\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKEN0 : PWM Output Mask Enable Bits\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKEN1 : PWM Output Mask Enable Bits\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKEN2 : PWM Output Mask Enable Bits\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKEN3 : PWM Output Mask Enable Bits\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKEN4 : PWM Output Mask Enable Bits\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKEN5 : PWM Output Mask Enable Bits\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AUTOCLR0 : Hardware Auto Clear ACMP0TEN\n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AUTOCLR1 : Hardware Auto Clear ACMP1TEN \n
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AOFFEN01 : ACMP1 Trigger Channel 0 One Cycle Output Off Enable Bit Setting this bit will force PWM channel 0 to output low lasting for at most one period cycle as long as ACMP1 trigger It This feature is usually in step motor application. Note: This function is only available for PWM0_CH0~PWM0_CH3.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AOFFEN11 : ACMP1 Trigger Channel 1 One Cycle Output Off Enable Bit Setting this bit will force PWM channel 1 to output low lasting for at most one period cycle as long as ACMP1 trigger It This feature is usually in step motor application. Note: This function is only available for PWM0_CH0~PWM0_CH3.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AOFFEN21 : ACMP1 Trigger Channel 2 One Cycle Output Off Enable Bit Setting this bit will force PWM channel 2 to output low lasting for at most one period cycle as long as ACMP1 trigger It This feature is usually in step motor application. Note: This function is only available for PWM0_CH0~PWM0_CH3.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AOFFEN31 : ACMP1 Trigger Channel 3 One Cycle Output Off Enable Bit Setting this bit will force PWM channel 3 to output low lasting for at most one period cycle as long as ACMP1 trigger It This feature is usually in step motor application. Note: This function is only available for PWM0_CH0~PWM0_CH3.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

A1POSSEL : ACMP1 Positive Input Source Select Bits\n
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1TEN : TMR1 Trigger PWM Function Enable Bit\nWhen this bit is set, TMR1 time-out event will update PWM_PHCHG with PHCHG_NXT register.\n
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACMP1TEN : ACMP1 Trigger Function Enable Bit\nNote: This bit will be auto cleared when ACMP1 trigger PWM if AUTOCLR1 is set.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AOFFEN00 : ACMP0 Trigger Channel 0 One Cycle Output Off Enable Bit Setting this bit will force PWM channel 0 to output low lasting for at most one period cycle as long as ACMP0 trigger It This feature is usually in step motor application. Note: This function is only available for PWM0_CH0~PWM0_CH3.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AOFFEN10 : ACMP0 Trigger Channel 1 One Cycle Output Off Enable Bit Setting this bit will force PWM channel 1 to output low lasting for at most one period cycle as long as ACMP0 trigger It This feature is usually in step motor application. Note: This function is only available for PWM0_CH0~PWM0_CH3.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AOFFEN20 : ACMP0 Trigger Channel 2 One Cycle Output Off Enable Bit Setting this bit will force PWM channel 2 to output low lasting for at most one period cycle as long as ACMP0 trigger It This feature is usually in step motor application. Note: This function is only available for PWM0_CH0~PWM0_CH3.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AOFFEN30 : ACMP0 Trigger Channel 3 One Cycle Output Off Enable Bit Setting this bit will force PWM channel 3 to output low lasting for at most one period cycle as long as ACMP0 trigger It This feature is usually in step motor application. Note: This function is only available for PWM0_CH0~PWM0_CH3.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

A0POSSEL : ACMP0 Positive Input Source Select Bits\n
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0TEN : TMR0 Trigger PWM Function Enable Bit\nWhen this bit is set, TMR0 time-out event will update PWM_PHCHG with PHCHG_NXT register.\n
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACMP0TEN : ACMP0 Trigger Function Enable Bit\nNote: This bit will be auto cleared when ACMP0 trigger PWM if AUTOCLR0 is set.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN0 : PWM Counter 0 Enable Start Run\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBGTRIOFF : Disable PWM Output Tri-state Under Debug Mode (Available In DEBUG Mode Only)\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PINV0 : PWM0_CH0 Output Inverter Enable Bit\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTMODE0 : PWM Counter 0 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause PERIOD0 and CMP0 cleared.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN1 : PWM Counter 1 Enable/Disable Start Run\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HCUPDT : Half Cycle Update Enable for Center-aligned Type\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PINV1 : PWM0_CH1 Output Inverter Enable Bit\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTMODE1 : PWM Counter 1 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause PERIOD1 and CMP1 cleared.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN2 : PWM Counter 2 Enable Start Run\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PINV2 : PWM0_CH2 Output Inverter Enable Bit\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTMODE2 : PWM Counter 2 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause PERIOD2 and CMP2 cleared.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN3 : PWM Counter 3 Enable Start Run\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PINV3 : PWM0_CH 3 Output Inverter Enable Bit\n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTMODE3 : PWM Counter 3 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause PERIOD3 and CMP3 cleared.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN4 : PWM Counter 4 Enable Start Run\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PINV4 : PWM0_CH4 Output Inverter Enable Bit\n
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTMODE4 : PWM Counter 4 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause PERIOD4 and CMP4 cleared.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN5 : PWM Counter 5 Enable Start Run\n
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ASYMEN : Asymmetric Mode In Center-aligned Type \n
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PINV5 : PWM0_CH5 Output Inverter Enable Bit\n
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTMODE5 : PWM Counter 5 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause PERIOD5 and CMP5 cleared.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DTCNT01 : Dead-time 0 Counter Enable Bit (PWM0_CH0 And PWM0_CH1 Pair For PWMA Group)\nNote: When the dead-time generator is enabled, the pair of PWM0_CH0 and PWM0_CH1 becomes a complementary pair for PWMA group.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DTCNT23 : Dead-time 2 Counter Enable Bit (PWM0_CH2 And PWM0_CH3 Pair For PWMB Group)\nNote: When the dead-time generator is enabled, the pair of PWM0_CH2 and PWM0_CH3 becomes a complementary pair for PWMB group.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DTCNT45 : Dead-time 4 Counter Enable Bit (PWM0_CH4 And PWM0_CH5 Pair For PWMC Group)\nNote: When the dead-time generator is enabled, the pair of PWM0_CH4 and PWM0_CH5 becomes a complementary pair for PWMC group.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTCLR : Clear PWM Counter Control Bit\nNote: It is automatically cleared by hardware.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE : PWM Operating Mode Select Bit\n
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GROUPEN : Group Function Enable Bit\n
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTTYPE : PWM Counter-aligned Type Select Bit\n
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MASKEND6 : PWM0_CH6 (GPIO P0.1) Output Mask Enable Bit\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MASKEND7 : PWM0_CH7 (GPIO P0.0) Output Mask Enable Bit\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POSCTL0 : Positive Input Control For ACMP0 Note: Register CMP0CR is described in Comparator Controller chapter.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POSCTL1 : Positive Input Control For ACMP1\nNote: Register CMP1CR is described in Comparator Controller chapter.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IFAEN : Interrupt Accumulation Function Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IFCNT : Interrupt Accumulation Counter \nWhen IFAEN is set, IFCNT will decrease when every ZIFn flag is set and when IFCNT reach to zero, the PWMn interrupt will occurred and IFCNT will reload itself.
bits : 4 - 7 (4 bit)
access : read-write