I2C_CTL

I2C_CLKDIV

I2C_TOCTL

I2C_ADDR1

I2C_ADDR2

I2C_ADDR3

I2C_ADDRMSK0

I2C_ADDRMSK1

I2C_ADDRMSK2

I2C_ADDRMSK3

I2C_CTL1

I2C_ADDR0

I2C_STATUS1

I2C_DAT

I2C_STATUS

AA : Assert Acknowledge Control Bit\n
bits : 2 - 2 (1 bit)
access : read-write

SI : I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware, and if bit INTEN (I2C_CTL[7]) is set, the I2C interrupt is requested. SI must be cleared by software. This bit can be cleared by software writing '1'.
bits : 3 - 3 (1 bit)
access : read-write

STO : I2C STOP Control Bit In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In Slave mode, setting STO resets I2C hardware to the defined not addressed Slave mode. This means it is NO LONGER in the Slave receiver mode to receive data from the master transmit device.
bits : 4 - 4 (1 bit)
access : read-write

STA : I2C START Control Bit\nSet STA to logic 1 to enter Master mode. I2C hardware sends a START or repeats the START condition to bus when the bus is free.
bits : 5 - 5 (1 bit)
access : read-write

I2CEN : I2C Controller Enable Bit\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTEN : Interrupt Enable Bit\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIVIDER : I2C Clock Divided Register\nNote: The minimum value of I2C_CLKDIV is 4.
bits : 0 - 7 (8 bit)
access : read-write

TOIF : Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: This bit can be cleared by software writing '1'.
bits : 0 - 0 (1 bit)
access : read-write

TOCURIEN : Time-out Counter Input Clock Divided By 4 Note: When enabled, the time-out period is extended 4 times.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TOCEN : Time-out Counter Enable Bit\nNote: When the 14-bit time-out counter is enabled, it will start counting when SI is cleared. Setting 1 to the SI flag will reset counter and re-start up counting after SI is cleared.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADDRMSK : I2C Address Mask Bits\n
bits : 1 - 7 (7 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKEN : Wake-up Enable Bit\nThe system can be woken up by I2C bus when the system is set into Power mode and the received data matched one of the addresses in Address Register.\nNote: Only I2C0 channel supports wake-up function. This bit is not valid on I2C1 channel.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TWOLVFIFO : Two-level Buffer Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NSTRETCH : No Stretch On The I2C Bus\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OVIEN : I2C Overrun Interrupt Control\nSetting OVIEN to 1 will send a interrupt to system when the TWOLVFF bit is enabled and there is overrun event in received buffer.\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

URIEN : I2C Under Run Interrupt Control\nSetting URIEN to 1 will send a interrupt to system when the TWOLVFF bit is enabled and there is under run event happened in transmitted buffer.\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GC : General Call Function Control\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADDR : I2C Address\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode, the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched.
bits : 1 - 7 (7 bit)
access : read-write

WKIF : I2C Wake-up Interrupt Flag When chip is woken up from Power-down mode by I2C, this bit is set to 1. This bit can be cleared by software writing 1 . Note: Only I2C0 channel supports wake-up function. This bit is not valid on I2C1 channel.
bits : 0 - 0 (1 bit)
access : read-write

FULL : I2C Two-level Buffer Full\n
bits : 1 - 1 (1 bit)
access : read-write

EMPTY : I2C Two-level Buffer Empty\n
bits : 2 - 2 (1 bit)
access : read-write

OVIF : I2C Overrun Status\n
bits : 3 - 3 (1 bit)
access : read-write

URIF : I2C Under Run Status\n
bits : 4 - 4 (1 bit)
access : read-write

DAT : I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of the I2C serial port.
bits : 0 - 7 (8 bit)
access : read-write

STATUS : I2C Status Register\n
bits : 0 - 7 (8 bit)
access : read-only