ADC_DAT (DAT)

ADC_CTL (CTL)

ADC_CHEN (CHEN)

ADC_CMP0 (CMP0)

ADC_CMP1 (CMP1)

ADC_STATUS (STATUS)

ADC_TRGDLY (TRGDLY)

ADC_EXTSMPT (EXTSMPT)

ADC_SEQCTL (SEQCTL)

ADC_SEQDAT1 (SEQDAT1)

ADC_SEQDAT2 (SEQDAT2)

RESULT : A/D Conversion Result\nThis field contains conversion result of ADC.
bits : 0 - 9 (10 bit)
access : read-only

OV : Over Run Flag\nIf converted data in RESULT[9:0] has not been read before the new conversion result is loaded to this register, OV is set to 1. It is cleared by hardware after the ADC_DAT register is read.\n
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

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VALID : Valid Flag \nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DAT register is read.\n
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

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ADCEN : A/D Converter Enable Bit\nNote: Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit to save power consumption.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

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ADCIEN : A/D Interrupt Enable Bit\nA/D conversion end interrupt request is generated if ADCIEN bit is set to 1.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

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HWTRGSEL : Hardware Trigger Source Select Bit\nNote: Software should disable TRGEN and SWTRG before change TRGS.
bits : 4 - 5 (2 bit)
access : read-write

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HWTRGCOND : Hardware External Trigger Condition\nThis bit decides whether the external pin STADC trigger event is falling or raising edge. The signal must be kept at stable state at least 4 PCLKs at high and low state for edge trigger.\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

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HWTRGEN : Hardware External Trigger Enable Bit\nEnable or disable triggering of A/D conversion by external STADC pin. If external trigger is enabled, the SWTRG bit can be set to 1 by the selected hardware trigger source.\n
bits : 8 - 8 (1 bit)
access : read-write

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SWTRG : Software Trigger A/D Conversion Start\nSWTRG bit can be set to 1 from two sources: software and external pin STADC. SWTRG will be cleared to 0 by hardware automatically after conversion complete.\n
bits : 11 - 11 (1 bit)
access : read-write

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CHEN0 : Analog Input Channel 0 Enable Bit\nNote: If software enables more than one channel, the channel with the smallest number will be selected and the other enabled channels will be ignored.
bits : 0 - 0 (1 bit)
access : read-write

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CHEN1 : Analog Input Channel 1 Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write

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CHEN2 : Analog Input Channel 2 Enable Bit\n
bits : 2 - 2 (1 bit)
access : read-write

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CHEN3 : Analog Input Channel 3 Enable Bit\n
bits : 3 - 3 (1 bit)
access : read-write

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CHEN4 : Analog Input Channel 4 Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write

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CHEN5 : Analog Input Channel 5 Enable Bit\n
bits : 5 - 5 (1 bit)
access : read-write

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CHEN6 : Analog Input Channel 6 Enable Bit\n
bits : 6 - 6 (1 bit)
access : read-write

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CHEN7 : Analog Input Channel 7 Enable Bit\n
bits : 7 - 7 (1 bit)
access : read-write

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CH7SEL : Analog Input Channel 7 Selection\nNote: When software selects the band-gap voltage as the analog input source of ADC channel 7, the ADC clock rate needs to be limited to lower than 300 kHz.
bits : 8 - 8 (1 bit)
access : read-write

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ADCMPEN : A/D Compare Enable Bit\nSet 1 to this bit to enable comparing CMPDAT (ADC_CMPx[25:16]) with specified channel conversion results when converted data is loaded into the ADC_DAT register.\n
bits : 0 - 0 (1 bit)
access : read-write

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ADCMPIE : A/D Compare Interrupt Enable Bit\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMCNT, ADCMPIE bit will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated.\n
bits : 1 - 1 (1 bit)
access : read-write

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CMPCOND : Compare Condition\nNote: When the internal counter reaches the value to (CMPMCNT+1), the ADCMPFx bit will be set.
bits : 2 - 2 (1 bit)
access : read-write

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CMPCH : Compare Channel Selection\nSet this field to select which channel's result to be compared.\nNote: Valid setting of this field is channel 0~7.
bits : 3 - 5 (3 bit)
access : read-write

CMPMCNT : Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1. When the internal counter reaches the value to (CMPMCNT+1), the ADCMPFx bit will be set.
bits : 8 - 11 (4 bit)
access : read-write

CMPDAT : Comparison Data\nThe 10-bit data is used to compare with conversion result of specified channel.
bits : 16 - 25 (10 bit)
access : read-write

ADIF : A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion. ADIF is set to 1 When A/D conversion ends.\nNote: This bit can be cleared to 0 by software writing 1.
bits : 0 - 0 (1 bit)
access : read-write

ADCMPF0 : A/D Compare Flag 0\nWhen the selected channel A/D conversion result meets the setting condition in ADC_CMP0, this bit is set to 1.\nNote: This bit can be cleared to 0 by software writing 1.
bits : 1 - 1 (1 bit)
access : read-write

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ADCMPF1 : A/D Compare Flag 1\nWhen the selected channel A/D conversion result meets the setting condition in ADC_CMP1, this bit is set to 1.\nNote: This bit can be cleared to 0 by software writing 1.
bits : 2 - 2 (1 bit)
access : read-write

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BUSY : BUSY/IDLE (Read Only)\nThis bit is mirror of as SWTRG bit in ADC_CTL\n
bits : 3 - 3 (1 bit)
access : read-only

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CHANNEL : Current Conversion Channel (Read Only)\n
bits : 4 - 6 (3 bit)
access : read-only

VALID : Data Valid Flag (Read Only)\nIt is a mirror of VALID bit in ADC_DAT register.
bits : 8 - 8 (1 bit)
access : read-only

OV : Overrun Flag (Read Only)\nIt is a mirror to OV bit in ADC_DAT register.
bits : 16 - 16 (1 bit)
access : read-only

DELAY : PWM Trigger Delay Timer\nSet this field will delay ADC start conversion time after PWM trigger.\nPWM trigger delay time is (4 * DELAY) * system clock.
bits : 0 - 7 (8 bit)
access : read-write

EXTSMPT : Additional ADC Sample Clock\nIf the ADC input is unstable, user can set this register to increase the sampling time to get a stable ADC input signal. The default sampling time is 1 ADC clocks. The additional clock number will be inserted to lengthen the sampling clock.\n
bits : 0 - 3 (4 bit)
access : read-write

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SEQEN : ADC Sequential Mode Enable Bit\nWhen ADC sequential mode is enabled, two of three ADC channels from 0 to 2 will automatically convert analog data in the sequence of channel [0, 1] or channel[1, 2] or channel[0, 2] defined by MODESEL (ADC_SEQCTL[3:2]).\n
bits : 0 - 0 (1 bit)
access : read-write

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SEQTYPE : ADC Sequential Mode Type\n
bits : 1 - 1 (1 bit)
access : read-write

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MODESEL : ADC Sequential Mode Selection\n
bits : 2 - 3 (2 bit)
access : read-write

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TRG1CTL : PWM Trigger Source Selection For TRG1CTL[3:2] Note: PWM trigger source is valid for 1-shunt and 2/3-shunt type.
bits : 8 - 11 (4 bit)
access : read-write

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TRG2CTL : PWM Trigger Source Selection For TRG2CTL[3:2]\nNote: PWM trigger source is valid for 1-shunt type.
bits : 16 - 19 (4 bit)
access : read-write

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RESULT : A/D PWM Sequential Mode Conversion Result\nThis field contains conversion result of ADC.
bits : 0 - 9 (10 bit)
access : read-only

OV : Over Run Flag\nIf converted data in RESULT[9:0] has not been read before the new conversion result is loaded to this register, OV is set to 1. It is cleared by hardware after the ADC_DAT register is read.\n
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

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VALID : Valid Flag\nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DAT register is read.\n
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.