\n
address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x28 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x54 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
USCI Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FUNMODE : Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
The USCI is disabled. All protocol related state machines are set to idle state
#001 : 1
The SPI protocol is selected
#010 : 2
The UART protocol is selected
#100 : 4
The I2C protocol is selected
End of enumeration elements list.
USCI Input Data Signal Configuration Register 0
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNCSEL : Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol, it is suggested this bit should be set as 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The un-synchronized signal can be taken as input for the data shift unit
#1 : 1
The synchronized signal can be taken as input for the data shift unit
End of enumeration elements list.
ININV : Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\nNote: In SPI protocol, it is suggested this bit should be set as 0.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The un-synchronized input signal will not be inverted
#1 : 1
The un-synchronized input signal will be inverted
End of enumeration elements list.
USCI Input Control Signal Configuration Register 0
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNCSEL : Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol, it is suggested this bit should be set as 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The un-synchronized signal can be taken as input for the data shift unit
#1 : 1
The synchronized signal can be taken as input for the data shift unit
End of enumeration elements list.
ININV : Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The un-synchronized input signal will not be inverted
#1 : 1
The un-synchronized input signal will be inverted
End of enumeration elements list.
USCI Input Clock Signal Configuration Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNCSEL : Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol, it is suggested this bit should be set as 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The un-synchronized signal can be taken as input for the data shift unit
#1 : 1
The synchronized signal can be taken as input for the data shift unit
End of enumeration elements list.
USCI Line Control Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSB : LSB First Transmission Selection
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first
#1 : 1
The LSB, the bit 0 of data buffer, will be transmitted/received first
End of enumeration elements list.
DATOINV : Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data output level is not inverted
#1 : 1
Data output level is inverted
End of enumeration elements list.
CTLOINV : Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: The control signal has different definitions in different protocol. In SPI protocol, the control signal means slave select signal.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
The control signal will be inverted before its output
End of enumeration elements list.
DWIDTH : Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0].
bits : 8 - 11 (4 bit)
access : read-write
USCI Transmit Data Register
address_offset : 0x30 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDAT : Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission. In order to avoid overwriting the transmit data, user has to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field.
bits : 0 - 15 (16 bit)
access : write-only
PORTDIR : Port Direction Control
bits : 16 - 16 (1 bit)
access : write-only
Enumeration:
#0 : 0
The data pin is configured as output mode
#1 : 1
The data pin is configured as input mode
End of enumeration elements list.
USCI Receive Data Register
address_offset : 0x34 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDAT : Received Data\nThis bit field monitors the received data which stored in receive data buffer.
bits : 0 - 15 (16 bit)
access : read-only
USCI Transmit/Receive Buffer Control Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXUDRIEN : Slave Transmit Under-run Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit under-run interrupt Disabled
#1 : 1
Transmit under-run interrupt Enabled
End of enumeration elements list.
TXCLR : Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
The transmit buffer is cleared. Should only be used while the buffer is not taking part in data traffic
End of enumeration elements list.
RXOVIEN : Receive Buffer Overrun Interrupt Enable Bit
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive overrun interrupt Disabled
#1 : 1
Receive overrun interrupt Enabled
End of enumeration elements list.
RXCLR : Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
The receive buffer is cleared. Should only be used while the buffer is not taking part in data traffic
End of enumeration elements list.
TXRST : Transmit Reset
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer
End of enumeration elements list.
RXRST : Receive Reset\nNote: It is cleared automatically after one PCLK cycle.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset the receive-related counters, state machine, and the content of receive shift register and data buffer
End of enumeration elements list.
USCI Transmit/Receive Buffer Status Register
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXEMPTY : Receive Buffer Empty Indicator (Read Only)
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receive buffer is not empty
#1 : 1
Receive buffer is empty
End of enumeration elements list.
RXFULL : Receive Buffer Full Indicator (Read Only)
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receive buffer is not full
#1 : 1
Receive buffer is full
End of enumeration elements list.
RXOVIF : Receive Buffer Over-run Interrupt Status\nThis bit indicates that a receive buffer overrun event has been detected. If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
A receive buffer overrun event has not been detected
#1 : 1
A receive buffer overrun event has been detected
End of enumeration elements list.
TXEMPTY : Transmit Buffer Empty Indicator (Read Only)
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit buffer is not empty
#1 : 1
Transmit buffer is empty and available for the next transmission datum
End of enumeration elements list.
TXFULL : Transmit Buffer Full Indicator (Read Only)
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit buffer is not full
#1 : 1
Transmit buffer is full
End of enumeration elements list.
TXUDRIF : Transmit Buffer Under-run Interrupt Status\nThis bit indicates that a transmit buffer under-run event has been detected. If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
A transmit buffer under-run event has not been detected
#1 : 1
A transmit buffer under-run event has been detected
End of enumeration elements list.
USCI Interrupt Enable Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXSTIEN : Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The transmit start interrupt Disabled
#1 : 1
The transmit start interrupt Enabled
End of enumeration elements list.
TXENDIEN : Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The transmit finish interrupt Disabled
#1 : 1
The transmit finish interrupt Enabled
End of enumeration elements list.
RXSTIEN : Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The receive start interrupt Disabled
#1 : 1
The receive start interrupt Enabled
End of enumeration elements list.
RXENDIEN : Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The receive end interrupt Disabled
#1 : 1
The receive end interrupt Enabled
End of enumeration elements list.
USCI PDMA Control Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMARST : PDMA Reset
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically
End of enumeration elements list.
TXPDMAEN : PDMA Transmit Channel Available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit PDMA function Disabled
#1 : 1
Transmit PDMA function Enabled
End of enumeration elements list.
RXPDMAEN : PDMA Receive Channel Available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive PDMA function Disabled
#1 : 1
Receive PDMA function Enabled
End of enumeration elements list.
PDMAEN : PDMA Mode Enable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA function Disabled
#1 : 1
PDMA function Enabled
End of enumeration elements list.
USCI Wake-up Control Register
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WKEN : Wake-up Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Wake-up function Disabled
#1 : 1
Wake-up function Enabled
End of enumeration elements list.
PDBOPT : Power Down Blocking Option
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately
#1 : 1
If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately
End of enumeration elements list.
USCI Wake-up Status Register
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WKF : Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write
USCI Protocol Control Register
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAVE : Slave Mode Selection
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Master mode
#1 : 1
Slave mode
End of enumeration elements list.
SLV3WIRE : Slave 3-wire Mode Selection (Slave Only)\nThe SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
4-wire bi-direction interface
#1 : 1
3-wire bi-direction interface
End of enumeration elements list.
SS : Slave Select Control (Master Only)\nIf AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select signal back to inactive state.\nNote: In SPI protocol, the internal slave select signal is active high.
bits : 2 - 2 (1 bit)
access : read-write
AUTOSS : Automatic Slave Select Function Enable (Master Only)
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave select signal will be controlled by the setting value of SS (USPI_PROTCTL[2]) bit
#1 : 1
Slave select signal will be generated automatically. The slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished
End of enumeration elements list.
SCLKMODE : Serial Bus Clock Mode\nThis bit field defines the SCLK idle status, data transmit, and data receive edge.
bits : 6 - 7 (2 bit)
access : read-write
SUSPITV : Suspend Interval (Master Only)\nThis bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle\nExample:
bits : 8 - 11 (4 bit)
access : read-write
TSMSEL : Transmit Data Mode Selection\nThis bit field describes how receive and transmit data is shifted in and out.\nOther values are reserved.\nNote: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically.
bits : 12 - 14 (3 bit)
access : read-write
SLVTOCNT : Slave Mode Time-out Period (Slave Only)\nIn Slave mode, this bit field is used for Slave time-out period. This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event. Writing 0x0 into this bit field will disable the Slave time-out function.\nExample: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK.
bits : 16 - 25 (10 bit)
access : read-write
TXUDRPOL : Transmit Under-run Data Polarity (for Slave)\nThis bit defines the transmitting data level when no data is available for transferring.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
The output data level is 0 if TX under run event occurs
#1 : 1
The output data level is 1 if TX under run event occurs
End of enumeration elements list.
PROTEN : SPI Protocol Enable Bit
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI Protocol Disabled
#1 : 1
SPI Protocol Enabled
End of enumeration elements list.
USCI Protocol Interrupt Enable Register
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSINAIEN : Slave Select Inactive Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave select inactive interrupt generation Disabled
#1 : 1
Slave select inactive interrupt generation Enabled
End of enumeration elements list.
SSACTIEN : Slave Select Active Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to active.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave select active interrupt generation Disabled
#1 : 1
Slave select active interrupt generation Enabled
End of enumeration elements list.
SLVTOIEN : Slave Time-out Interrupt Enable Bit\nIn SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The Slave time-out interrupt Disabled
#1 : 1
The Slave time-out interrupt Enabled
End of enumeration elements list.
SLVBEIEN : Slave Mode Bit Count Error Interrupt Enable Bit\nIf data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]), bit count error event occurs.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The Slave mode bit count error interrupt Disabled
#1 : 1
The Slave mode bit count error interrupt Enabled
End of enumeration elements list.
USCI Protocol Status Register
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXSTIF : Transmit Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit start event did not occur
#1 : 1
Transmit start event occurred
End of enumeration elements list.
TXENDIF : Transmit End Interrupt Flag\nNote: It is cleared by software write 1 to this bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit end event did not occur
#1 : 1
Transmit end event occurred
End of enumeration elements list.
RXSTIF : Receive Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive start event did not occur
#1 : 1
Receive start event occurred
End of enumeration elements list.
RXENDIF : Receive End Interrupt Flag\nNote: It is cleared by software write 1 to this bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive end event did not occur
#1 : 1
Receive end event occurred
End of enumeration elements list.
SLVTOIF : Slave Time-out Interrupt Flag (for Slave Only)\nNote: It is cleared by software write 1 to this bit
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave time-out event did not occur
#1 : 1
Slave time-out event occurred
End of enumeration elements list.
SLVBEIF : Slave Bit Count Error Interrupt Flag (for Slave Only)\nNote: It is cleared by software write 1 to this bit.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave bit count error event did not occur
#1 : 1
Slave bit count error event occurred
End of enumeration elements list.
SSINAIF : Slave Select Inactive Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to inactive. It is cleared by software writes 1 to this bit\nNote: The internal slave select signal is active high.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The slave select signal has not changed to inactive
#1 : 1
The slave select signal has changed to inactive
End of enumeration elements list.
SSACTIF : Slave Select Active Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to active. It is cleared by software writes one to this bit\nNote: The internal slave select signal is active high.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
The slave select signal has not changed to active
#1 : 1
The slave select signal has changed to active
End of enumeration elements list.
SSLINE : Slave Select Line Bus Status (Read Only)\nThis bit is only available in Slave mode. It used to monitor the current status of the input slave select signal on the bus.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
The slave select line status is 0
#1 : 1
The slave select line status is 1
End of enumeration elements list.
BUSY : Busy Status (Read Only)
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
SPI is in idle state
#1 : 1
SPI is in busy state
End of enumeration elements list.
SLVUDR : Slave Mode Transmit Under-run Status (Read Only)\nIn Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1. This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not.
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
#0 : 0
Slave transmit under-run event does not occur
#1 : 1
Slave transmit under-run event occurs
End of enumeration elements list.
USCI Baud Rate Generator Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RCLKSEL : Reference Clock Source Selection\nThis bit selects the source of reference clock (fREF_CLK).
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Peripheral device clock fPCLK
#1 : 1
Reserved
End of enumeration elements list.
PTCLKSEL : Protocol Clock Source Selection\nThis bit selects the source of protocol clock (fPROT_CLK).
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reference clock fREF_CLK
#1 : 1
fREF_CLK2 (its frequency is half of fREF_CLK)
End of enumeration elements list.
SPCLKSEL : Sample Clock Source Selection\nThis bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
fDIV_CLK
#01 : 1
fPROT_CLK
#10 : 2
fSCLK
#11 : 3
fREF_CLK
End of enumeration elements list.
TMCNTEN : Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Time measurement counter Disabled
#1 : 1
Time measurement counter Enabled
End of enumeration elements list.
TMCNTSRC : Time Measurement Counter Clock Source Selection
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Time measurement counter with fPROT_CLK
#1 : 1
Time measurement counter with fDIV_CLK
End of enumeration elements list.
CLKDIV : Clock Divider
bits : 16 - 25 (10 bit)
access : read-write
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