\n
address_offset : 0x0 Bytes (0x0)
size : 0x54 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x200 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x58 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
Host Controller Revision Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REV : Revision Number\nIndicates the Open HCI Specification revision number implemented by the Hardware. Host Controller supports 1.1 specification.
bits : 0 - 7 (8 bit)
access : read-only
Host Controller Interrupt Enable Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SO : Scheduling Overrun Enable Bit\nWrite Operation:
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nInterrupt generation due to SO (HcInterruptStatus[0]) Disabled
#1 : 1
Interrupt generation due to SO (HcInterruptStatus[0]) Enabled
End of enumeration elements list.
WDH : Write Back Done Head Enable Bit\nWrite Operation:
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nInterrupt generation due to WDH (HcInterruptStatus[1]) Disabled
#1 : 1
Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled
End of enumeration elements list.
SF : Start of Frame Enable Bit\nWrite Operation:
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nInterrupt generation due to SF (HcInterruptStatus[2]) Disabled
#1 : 1
Interrupt generation due to SF (HcInterruptStatus[2]) Enabled
End of enumeration elements list.
RD : Resume Detected Enable Bit\nWrite Operation:
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nInterrupt generation due to RD (HcInterruptStatus[3]) Disabled
#1 : 1
Interrupt generation due to RD (HcInterruptStatus[3]) Enabled
End of enumeration elements list.
FNO : Frame Number Overflow Enable Bit\nWrite Operation:
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nInterrupt generation due to FNO (HcInterruptStatus[5]) Disabled
#1 : 1
Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled
End of enumeration elements list.
RHSC : Root Hub Status Change Enable Bit\nWrite Operation:
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nInterrupt generation due to RHSC (HcInterruptStatus[6]) Disabled
#1 : 1
Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled
End of enumeration elements list.
MIE : Master Interrupt Enable Bit\nThis bit is a global interrupt enable. A write of '1' allows interrupts to be enabled via the specific enable bits listed above.\nWrite Operation:
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nInterrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high
#1 : 1
Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high
End of enumeration elements list.
Host Controller Interrupt Disable Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SO : Scheduling Overrun Disable Bit\nWrite Operation:
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nInterrupt generation due to SO (HcInterruptStatus[0]) Disabled
#1 : 1
Interrupt generation due to SO (HcInterruptStatus[0]) Disabled.\nInterrupt generation due to SO (HcInterruptStatus[0]) Enabled
End of enumeration elements list.
WDH : Write Back Done Head Disable Bit\nWrite Operation:
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nInterrupt generation due to WDH (HcInterruptStatus[1]) Disabled
#1 : 1
Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled.\nInterrupt generation due to WDH (HcInterruptStatus[1]) Enabled
End of enumeration elements list.
SF : Start of Frame Disable Bit\nWrite Operation:
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nInterrupt generation due to SF (HcInterruptStatus[2]) Disabled
#1 : 1
Interrupt generation due to SF (HcInterruptStatus[2]) Disabled.\nInterrupt generation due to SF (HcInterruptStatus[2]) Enabled
End of enumeration elements list.
RD : Resume Detected Disable Bit\nWrite Operation:
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nInterrupt generation due to RD (HcInterruptStatus[3]) Disabled
#1 : 1
Interrupt generation due to RD (HcInterruptStatus[3]) Disabled.\nInterrupt generation due to RD (HcInterruptStatus[3]) Enabled
End of enumeration elements list.
FNO : Frame Number Overflow Disable Bit\nWrite Operation:
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nInterrupt generation due to FNO (HcInterruptStatus[5]) Disabled
#1 : 1
Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled.\nInterrupt generation due to FNO (HcInterruptStatus[5]) Enabled
End of enumeration elements list.
RHSC : Root Hub Status Change Disable Bit\nWrite Operation:
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nInterrupt generation due to RHSC (HcInterruptStatus[6]) Disabled
#1 : 1
Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled.\nInterrupt generation due to RHSC (HcInterruptStatus[6]) Enabled
End of enumeration elements list.
MIE : Master Interrupt Disable Bit\nGlobal interrupt disable. Writing '1' to disable all interrupts.\nWrite Operation:
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nInterrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high
#1 : 1
Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled if the corresponding bit in HcInterruptEnable is high.\nInterrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high
End of enumeration elements list.
Host Controller Communication Area Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCCA : Host Controller Communication Area\nPointer to indicate base address of the Host Controller Communication Area (HCCA).
bits : 8 - 31 (24 bit)
access : read-write
Host Controller Period Current ED Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCED : Periodic Current ED\nPointer to indicate physical address of the current Isochronous or Interrupt Endpoint Descriptor.
bits : 4 - 31 (28 bit)
access : read-write
Host Controller Control Head ED Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHED : Control Head ED\nPointer to indicate physical address of the first Endpoint Descriptor of the Control list.
bits : 4 - 31 (28 bit)
access : read-write
Host Controller PHY Control Register
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STBYEN : USB Transceiver Standby Enable Bit\nThis bit controls if USB transceiver could enter the standby mode to reduce power consumption.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
The USB transceiver would never enter the standby mode
#1 : 1
The USB transceiver will enter standby mode while port is in power off state (port power is inactive)
End of enumeration elements list.
Host Controller Miscellaneous Control Register
address_offset : 0x204 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ABORT : AHB Bus ERROR Response\nThis bit indicates there is an ERROR response received in AHB bus.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No ERROR response received
#1 : 1
ERROR response received
End of enumeration elements list.
OCAL : Over Current Active Low\nThis bit controls the polarity of over current flag from external power IC.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Over current flag is high active
#1 : 1
Over current flag is low active
End of enumeration elements list.
PPCAL : Port Power Control Active Low\nThis bit controls the polarity of port power control to external power IC.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Port power control is high active
#1 : 1
Port power control is low active
End of enumeration elements list.
DPRT1 : Disable Port 1\nThis bit controls if the connection between USB host controller and transceiver of port 1 is disabled. If the connection is disabled, the USB host controller will not recognize any event of USB bus.\nSet this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
The connection between USB host controller and transceiver of port 1 Enabled
#1 : 1
The connection between USB host controller and transceiver of port 1 Disabled and the transceiver of port 1 will also be forced into the standby mode
End of enumeration elements list.
Host Controller Control Current ED Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCED : Control Current Head ED\nPointer to indicate the physical address of the current Endpoint Descriptor of the Control list.
bits : 4 - 31 (28 bit)
access : read-write
Host Controller Bulk Head ED Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BHED : Bulk Head ED\nPointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list.
bits : 4 - 31 (28 bit)
access : read-write
Host Controller Bulk Current ED Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BCED : Bulk Current Head ED\nPointer to indicate the physical address of the current endpoint of the Bulk list.
bits : 4 - 31 (28 bit)
access : read-write
Host Controller Done Head Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DH : Done Head\nPointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue.
bits : 4 - 31 (28 bit)
access : read-write
Host Controller Frame Interval Register
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FI : Frame Interval\nThis field specifies the length of a frame as (bit times - 1). For 12,000 bit times in a frame, a value of 11,999 is stored here.
bits : 0 - 13 (14 bit)
access : read-write
FSMPS : FS Largest Data Packet\nThis field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame.
bits : 16 - 30 (15 bit)
access : read-write
FIT : Frame Interval Toggle\nThis bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmInterval[13:0]).
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Host Controller Driver didn't load new value into FI (HcFmInterval[13:0])
#1 : 1
Host Controller Driver loads a new value into FI (HcFmInterval[13:0])
End of enumeration elements list.
Host Controller Frame Remaining Register
address_offset : 0x38 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FR : Frame Remaining\nWhen the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period. When the count reaches 0, (end of frame) the counter reloads with Frame Interval. In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL.
bits : 0 - 13 (14 bit)
access : read-only
FRT : Frame Remaining Toggle\nThis bit is loaded from the FIT (HcFmInterval[31]) whenever FR (HcFmRemaining[13:0]) reaches 0.
bits : 31 - 31 (1 bit)
access : read-only
Host Controller Frame Number Register
address_offset : 0x3C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FN : Frame Number\nThis 16-bit incrementing counter field is incremented coincident with the re-load of FR (HcFmRemaining[13:0]). The count rolls over from 'FFFFh' to '0h.'
bits : 0 - 15 (16 bit)
access : read-only
Host Controller Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CBSR : Control Bulk Service Ratio\nThis specifies the service ratio between Control and Bulk EDs. Before processing any of the non-periodic lists, HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs. The internal count will be retained when crossing the frame boundary. In case of reset, HCD is responsible for restoring this\nValue.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Number of Control EDs over Bulk EDs served is 1:1
#01 : 1
Number of Control EDs over Bulk EDs served is 2:1
#10 : 2
Number of Control EDs over Bulk EDs served is 3:1
#11 : 3
Number of Control EDs over Bulk EDs served is 4:1
End of enumeration elements list.
PLE : Periodic List Enable Bit
When set, this bit enables processing of the Periodic (interrupt and isochronous) list. The Host Controller checks this bit prior to attempting any periodic transfers in a frame.
Note: To enable the processing of the Isochronous list, user has to set both PLE and IE (HcControl[3]) high.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Processing of the Periodic (Interrupt and Isochronous) list after next SOF (Start-Of-Frame) Disabled
#1 : 1
Processing of the Periodic (Interrupt and Isochronous) list in the next frame Enabled
End of enumeration elements list.
IE : Isochronous List Enable Bit\nBoth ISOEn and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list. Either ISOEn or PLE (HcControl[2]) is low disables Host Controller to process the Isochronous list.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Processing of the Isochronous list after next SOF (Start-Of-Frame) Disabled
#1 : 1
Processing of the Isochronous list in the next frame Enabled, if the PLE (HcControl[2]) is high, too
End of enumeration elements list.
CLE : Control List Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Processing of the Control list after next SOF (Start-Of-Frame) Disabled
#1 : 1
Processing of the Control list in the next frame Enabled
End of enumeration elements list.
BLE : Bulk List Enable Bit
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Processing of the Bulk list after next SOF (Start-Of-Frame) Disabled
#1 : 1
Processing of the Bulk list in the next frame Enabled
End of enumeration elements list.
HCFS : Host Controller Functional State\nThis field sets the Host Controller state. The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port. States are:
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
USBSUSPEND
#01 : 1
USBOPERATIONAL
#10 : 2
USBRESUME
#11 : 3
USBRESET
End of enumeration elements list.
Host Controller Periodic Start Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Periodic Start\nThis field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin.
bits : 0 - 13 (14 bit)
access : read-write
Host Controller Low-speed Threshold Register
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LST : Low-speed Threshold
bits : 0 - 11 (12 bit)
access : read-write
Host Controller Root Hub Descriptor A Register
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDP : Number Downstream Ports\nUSB host control supports two downstream ports and only one port is available in this series of chip.
bits : 0 - 7 (8 bit)
access : read-write
PSM : Power Switching Mode\nThis bit is used to specify how the power switching of the Root Hub ports is controlled.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Global Switching
#1 : 1
Individual Switching
End of enumeration elements list.
OCPM : over Current Protection Mode\nThis bit describes how the over current status for the Root Hub ports reported. This bit is only valid when NOCP (HcRhDescriptorA[12]) is cleared.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Global Over current
#1 : 1
Individual Over current
End of enumeration elements list.
NOCP : No over Current Protection\nThis bit describes how the over current status for the Root Hub ports reported.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Over current status is reported
#1 : 1
Over current status is not reported
End of enumeration elements list.
Host Controller Root Hub Descriptor B Register
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PPCM : Port Power Control Mask\nGlobal power switching. This field is only valid if PowerSwitchingMode is set (individual port switching). When set, the port only responds to individual port power switching commands (Set/ClearPortPower). When cleared, the port only responds to global power switching commands (Set/ClearGlobalPower).\nNote: PPCM[15:2] and PPCM[0] are reserved.
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
0 : 0
Port power controlled by global power switching
1 : 1
Port power controlled by port power switching
End of enumeration elements list.
Host Controller Root Hub Status Register
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPS : Clear Global Power
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear global power
End of enumeration elements list.
OCI : over Current Indicator\nThis bit reflects the state of the over current status pin. This field is only valid if NOCP (HcRhDesA[12]) and OCPM (HcRhDesA[11]) are cleared.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No over current condition
#1 : 1
Over current condition
End of enumeration elements list.
DRWE : Device Remote Wakeup Enable Bit\nThis bit controls if port's Connect Status Change as a remote wake-up event.\nWrite Operation:
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nConnect Status Change as a remote wake-up event Disabled
#1 : 1
Connect Status Change as a remote wake-up event Enabled
End of enumeration elements list.
LPSC : Set Global Power
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Set global power
End of enumeration elements list.
OCIC : over Current Indicator Change\nThis bit is set by hardware when a change has occurred in OCI (HcRhStatus[1]).\nWrite 1 to clear this bit to zero.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
OCI (HcRhStatus[1]) didn't change
#1 : 1
OCI (HcRhStatus[1]) change
End of enumeration elements list.
CRWE : Clear Remote Wake-up Enable Bit\nThis bit is use to clear DRWE (HcRhStatus[15]).\nThis bit always read as zero.\nWrite Operation:
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear DRWE (HcRhStatus[15])
End of enumeration elements list.
Host Controller Root Hub Port Status [1]
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCS : CurrentConnectStatus (Read) or ClearPortEnable Bit (Write)\nWrite Operation:
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nNo device connected
#1 : 1
Clear port enable.\nDevice connected
End of enumeration elements list.
PES : Port Enable Status\nWrite Operation:
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nPort Disabled
#1 : 1
Set port enable.\nPort Enabled
End of enumeration elements list.
PSS : Port Suspend Status\nThis bit indicates the port is suspended\nWrite Operation:
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nPort is not suspended
#1 : 1
Set port suspend.\nPort is selectively suspended
End of enumeration elements list.
POCI : Port over Current Indicator (Read) or Clear Port Suspend (Write)\nThis bit reflects the state of the over current status pin dedicated to this port. This field is only valid if NOCP (HcRhDescriptorA[12]) is cleared and OCPM (HcRhDescriptorA[11]) is set.\nThis bit is also used to initiate the selective result sequence for the port.\nWrite Operation:
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nNo over current condition
#1 : 1
Clear port suspend.\nOver current condition
End of enumeration elements list.
PRS : Port Reset Status\nThis bit reflects the reset state of the port.\nWrite Operation:
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nPort reset signal is not active
#1 : 1
Set port reset.\nPort reset signal is active
End of enumeration elements list.
PPS : Port Power Status\nThis bit reflects the power state of the port regardless of the power switching mode.\nWrite Operation:
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nPort power is Disabled
#1 : 1
Port Power Enabled.\nPort power is Enabled
End of enumeration elements list.
LSDA : Low Speed Device Attached (Read) or Clear Port Power (Write)\nThis bit defines the speed (and bud idle) of the attached device. It is only valid when CCS (HcRhPortStatus1[0]) is set.\nThis bit is also used to clear port power.\nWrite Operation:
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nFull Speed device
#1 : 1
Clear PPS (HcRhPortStatus1[8]).\nLow-speed device
End of enumeration elements list.
CSC : Connect Status Change\nThis bit indicates connect or disconnect event has been detected (CCS (HcRhPortStatus1[0]) changed).\nWrite 1 to clear this bit to zero.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
No connect/disconnect event (CCS (HcRhPortStatus1[0]) didn't change)
#1 : 1
Hardware detection of connect/disconnect event (CCS (HcRhPortStatus1[0]) changed)
End of enumeration elements list.
PESC : Port Enable Status Change\nThis bit indicates that the port has been disabled (PES (HcRhPortStatus1[1]) cleared) due to a hardware event.\nWrite 1 to clear this bit to zero.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PES (HcRhPortStatus1[1]) didn't change
#1 : 1
PES (HcRhPortStatus1[1]) changed
End of enumeration elements list.
PSSC : Port Suspend Status Change\nThis bit indicates the completion of the selective resume sequence for the port.\nWrite 1 to clear this bit to zero.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Port resume is not completed
#1 : 1
Port resume completed
End of enumeration elements list.
OCIC : Port over Current Indicator Change\nThis bit is set when POCI (HcRhPortStatus1[3]) changes.\nWrite 1 to clear this bit to zero.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
POCI (HcRhPortStatus1[3]) didn't change
#1 : 1
POCI (HcRhPortStatus1[3]) changes
End of enumeration elements list.
PRSC : Port Reset Status Change\nThis bit indicates that the port reset signal has completed.\nWrite 1 to clear this bit to zero.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Port reset is not complete
#1 : 1
Port reset is complete
End of enumeration elements list.
Host Controller Command Status Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCR : Host Controller Reset\nThis bit is set to initiate the software reset of Host Controller. This bit is cleared by the Host Controller, upon completed of the reset operation.\nThis bit, when set, didn't reset the Root Hub and no subsequent reset signaling be asserted to its downstream ports.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Host Controller is not in software reset state
#1 : 1
Host Controller is in software reset state
End of enumeration elements list.
CLF : Control List Filled\nSet high to indicate there is an active TD on the Control List. It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No active TD found or Host Controller begins to process the head of the Control list
#1 : 1
An active TD added or found on the Control list
End of enumeration elements list.
BLF : Bulk List Filled\nSet high to indicate there is an active TD on the Bulk list. This bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No active TD found or Host Controller begins to process the head of the Bulk list
#1 : 1
An active TD added or found on the Bulk list
End of enumeration elements list.
SOC : Schedule Overrun Count\nThese bits are incremented on each scheduling overrun error. It is initialized to 00b and wraps around at 11b. This will be incremented when a scheduling overrun is detected even if SO (HcInterruptStatus[0]) has already been set.
bits : 16 - 17 (2 bit)
access : read-write
Host Controller Interrupt Status Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SO : Scheduling Overrun\nSet when the List Processor determines a Schedule Overrun has occurred.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Schedule Overrun didn't occur
#1 : 1
Schedule Overrun has occurred
End of enumeration elements list.
WDH : Write Back Done Head\nSet after the Host Controller has written HcDoneHead to HccaDoneHead. Further updates of the HccaDoneHead will not occur until this bit has been cleared.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Host Controller didn't update HccaDoneHead
#1 : 1
Host Controller has written HcDoneHead to HccaDoneHead
End of enumeration elements list.
SF : Start of Frame\nSet when the Frame Management functional block signals a 'Start of Frame' event. Host Control generates a SOF token at the same time.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not the start of a frame
#1 : 1
Indicate the start of a frame and Host Controller generates a SOF token
End of enumeration elements list.
RD : Resume Detected\nSet when Host Controller detects resume signaling on a downstream port.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No resume signaling detected on a downstream port
#1 : 1
Resume signaling detected on a downstream port
End of enumeration elements list.
FNO : Frame Number Overflow\nThis bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The bit 15 of Frame Number didn't change
#1 : 1
The bit 15 of Frame Number changes from 1 to 0 or from 0 to 1
End of enumeration elements list.
RHSC : Root Hub Status Change\nThis bit is set when the content of HcRhStatus or the content of HcRhPortStatus1 register has changed.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The content of HcRhStatus and the content of HcRhPortStatus1 register didn't change
#1 : 1
The content of HcRhStatus or the content of HcRhPortStatus1 register has changed
End of enumeration elements list.
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