\n
address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x30 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
System Power Down Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HXT_EN : HXT Control\nThis is a protected register. Please refer to open lock sequence to program it.\nThe bit default value is set by flash controller user configuration register config0 [26]. \nHXT is disabled by default.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
LXT_EN : LXT Control\nThis is a protected register. Please refer to open lock sequence to program it.\nLXT is disabled by default.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
HIRC_EN : HIRC Control\nThis is a protected register. Please refer to open lock sequence to program it.\nHIRC is enabled by default.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
LIRC_EN : LIRC Control\nThis is a protected register. Please refer to open lock sequence to program it.\nLIRC is enabled by default.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
WK_DLY : Wake-up Delay Counter Enable\nThis is a protected register. Please refer to open lock sequence to program it.\nWhen chip wakes up from Power-down mode, the clock control will delay 4096 clock cycles to wait HXT stable or 16 clock cycles to wait HIRC stable.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Delay clock cycle delay Disabled
#1 : 1
Delay clock cycle delay Enabled
End of enumeration elements list.
PD_WK_IE : Power-down Mode Wake-up Interrupt Enable \nThis is a protected register. Please refer to open lock sequence to program it.\nPD_WK_INT will be set if both PD_WK_IS and PD_WK_IE are high.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PD_EN : Chip Power-down mode Enable Bit
This is a protected register. Please refer to open lock sequence to program it.
When CPU sets this bit, the chip power down is enabled and chip will not enter Power-down mode until CPU sleep mode is also active.
When chip wakes up from Power-down mode, this bit will be auto cleared.
When chip is in Power-down mode, the LDO, HXT and HIRC will be disabled, but LXT and LIRC are not controlled by Power-down mode.
When power down, the PLL and system clock (CPU, HCLKx and PCLKx) are also disabled no matter the Clock Source selection. Peripheral clocks are not controlled by this bit, if peripheral Clock Source is from LXT or LIRC.
In Power-down mode, flash macro power is ON.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip operated in Normal mode
#1 : 1
Chip power down Enabled
End of enumeration elements list.
HXT_SELXT : HXT SELXT\nThis is a protected register. Please refer to open lock sequence to program it.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
High frequency crystal loop back path Disabled. It is used for external oscillator
#1 : 1
High frequency crystal loop back path Enabled. It is used for external crystal
End of enumeration elements list.
HXT_GAIN : HXT Gain Control Bit\nThis is a protected register. Please refer to open lock sequence to program it.\nGain control is used to enlarge the gain of crystal to make sure crystal wok normally. If gain control is enabled, crystal will consume more power than gain control off. \nFor 4MHz to 16MHz crystal.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Gain control Disabled. It means HXT gain is always high
#1 : 1
Gain control Enabled. HXT gain will be high lasting 2ms then low. This is for power saving
End of enumeration elements list.
LXT_SCNT : LXT Stable Time Control\nThis is a protected register. Please refer to open lock sequence to program it.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Delay 4096 LXT before LXT output
#1 : 1
Delay 8192 LXT before LXT output
End of enumeration elements list.
HXT_HF_ST : HXT_HF_ST
bits : 11 - 12 (2 bit)
access : read-write
Clock Source Select Control Register 0
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLK_S : HCLK Clock Source Selection.
bits : 0 - 2 (3 bit)
access : read-write
Clock Source Select Control Register 1
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART_S : UART 0/1 Clock Source Selection (UART0 and UART1 Use the Same Clock Source Selection)
bits : 0 - 1 (2 bit)
access : read-write
ADC_S : ADC Clock Source Selection
bits : 2 - 3 (2 bit)
access : read-write
PWM0_CH01_S : PWM0 channel 0 and channel 1 Clock Source Selection
bits : 4 - 5 (2 bit)
access : read-write
PWM0_CH23_S : PWM0 channel 2 and channel 3 Clock Source Selection
bits : 6 - 7 (2 bit)
access : read-write
TMR0_S : Timer0 Clock Source Selection\n
bits : 8 - 10 (3 bit)
access : read-write
TMR1_S : Timer1 Clock Source Selection
bits : 12 - 14 (3 bit)
access : read-write
LCD_S : LCD Clock Source Selection
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Source from LXT
#1 : 1
Reserved
End of enumeration elements list.
Clock Source Select Control Register 2
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRQDIV_S : Clock Divider Clock Source Selection
bits : 2 - 3 (2 bit)
access : read-write
PWM1_CH01_S : PWM1 channel 0 and channel 1 Clock Source Selection
bits : 4 - 5 (2 bit)
access : read-write
PWM1_CH23_S : PWM1 channel 2 and channel 2 Clock Source Selection
bits : 6 - 7 (2 bit)
access : read-write
TMR2_S : Timer2 Clock Source Selection
bits : 8 - 10 (3 bit)
access : read-write
TMR3_S : Timer3 Clock Source Selection
bits : 12 - 14 (3 bit)
access : read-write
I2S_S : I2S Clock Source Selection
bits : 16 - 17 (2 bit)
access : read-write
SC_S : SC Clock Source Selection
bits : 18 - 19 (2 bit)
access : read-write
SPI0_S : SPI0 Clock Source Selection
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL
#1 : 1
HCLK
End of enumeration elements list.
SPI1_S : SPI1 Clock Source Selection
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL
#1 : 1
HCLK
End of enumeration elements list.
SPI2_S : SPI2 Clock Source Selection
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL
#1 : 1
HCLK
End of enumeration elements list.
Clock Divider Number Register 0
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLK_N : HCLK clock divide number from HCLK clock source
bits : 0 - 3 (4 bit)
access : read-write
USB_N : USB clock divide number from PLL clock
bits : 4 - 7 (4 bit)
access : read-write
UART_N : UART clock divide number from UART clock source
bits : 8 - 11 (4 bit)
access : read-write
I2S_N : I2S clock divide number from I2S clock source
bits : 12 - 15 (4 bit)
access : read-write
ADC_N : ADC clock divide number from ADC clock source
bits : 16 - 23 (8 bit)
access : read-write
SC0_N : SC 0 clock divide number from SC 0 clock source
bits : 28 - 31 (4 bit)
access : read-write
Clock Divider Number Register 1
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SC1_N : SC 1 clock divide number from SC 1 clock source
bits : 0 - 3 (4 bit)
access : read-write
SC2_N : SC 2 clock divide number from SC2 clock source
bits : 4 - 7 (4 bit)
access : read-write
PLL Control Register
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FB_DV : PLL Feedback Divider Control Pins \nRefer to the formulas below the table.\nThe range of FB_DV is from 0 to 63.
bits : 0 - 4 (5 bit)
access : read-write
IN_DV : PLL Input Divider Control Pins\nRefer to the formulas below the table.
bits : 8 - 9 (2 bit)
access : read-write
OUT_DV : PLL Output Divider Control Pins \nRefer to the formulas below the table. This bit MUST be 0 for PLL output low deviation.
bits : 12 - 12 (1 bit)
access : read-write
PD : Power-down mode.
If set the PD_EN bit 1 in PWR_CTL register, the PLL will enter Power-down mode too
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL is in normal mode
#1 : 1
PLL is in power-down mode (default)
End of enumeration elements list.
PLL_SRC : PLL Source Clock Select
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL source clock from HXT
#1 : 1
PLL source clock from HIRC
End of enumeration elements list.
Frequency Divider Control Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSEL : Divider Output Frequency Selection Bits\nThe formula of output frequency is\nWhere Fin is the input clock frequency, Fout is the frequency of divider output clock and N is the 4-bit value of FSEL[3:0].
bits : 0 - 3 (4 bit)
access : read-write
FDIV_EN : Frequency Divider Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frequency Divider Disabled
#1 : 1
Frequency Divider Enabled
End of enumeration elements list.
Wake-up interrupt status
address_offset : 0x30 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PD_WK_IS : Wake-up Interrupt Sstatus in chip Power-down Mode\nThis bit indicates that some event resumes chip from Power-down mode \nThe status is set if external interrupts, UART, GPIO, RTC, USB, SPI, Timer, WDT, and BOD wake-up occurred.\nWrite 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-only
AHB Devices Clock Enable Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO_EN : GPIO Controller Clock Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
DMA_EN : DMA Controller Clock Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
ISP_EN : Flash ISP Controller Clock Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
EBI_EN : EBI Controller Clock Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
SRAM_EN : SRAM Controller Clock Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
TICK_EN : System Tick Clock Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
APB Devices Clock Enable Control Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_EN : Watchdog Timer Clock Enable Control. \nThis is a protected register. Please refer to open lock sequence to program it.\nThis bit is used to control the WDT APB clock only, The WDT engine Clock Source is from LIRC.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
RTC_EN : Real-Time-Clock Clock Enable Control. \nThis bit is used to control the RTC APB clock only, The RTC engine Clock Source is from LXT.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
TMR0_EN : Timer0 Clock Enable Control
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
TMR1_EN : Timer1 Clock Enable Control
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
TMR2_EN : Timer2 Clock Enable Control
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
TMR3_EN : Timer3 Clock Enable Control
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
FDIV_EN : Frequency Divider Output Clock Enable Control
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
SC2_EN : SmartCard 2 Clock Enable Control.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
I2C0_EN : I2C0 Clock Enable Control.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
I2C1_EN : I2C1 Clock Enable Control.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
SPI0_EN : SPI0 Clock Enable Control.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
SPI1_EN : SPI1 Clock Enable Control.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
SPI2_EN : SPI2 Clock Enable Control.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
UART0_EN : UART0 Clock Enable Control.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
UART1_EN : UART1 Clock Enable Control.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWM0_CH01_EN : PWM0 Channel 0 and Channel 1Clock Enable Control.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWM0_CH23_EN : PWM0 Channel 2 and Channel 3 Clock Enable Control.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWM1_CH01_EN : PWM1 Channel 0 and Channel 1 Clock Enable Control.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWM1_CH23_EN : PWM1 Channel 2 and Channel 3 Clock Enable Control.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
DAC_EN : 12-bit DAC Clock Enable Control
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
LCD_EN : LCD controller Clock Enable Control
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
USBD_EN : USB FS Device Controller Clock Enable Control
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
ADC_EN : Analog-Digital-Converter (ADC) Clock Enable Control.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
I2S_EN : I2S Clock Enable Control.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
SC0_EN : SmartCard 0 Clock Enable Control.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
SC1_EN : SmartCard 1 Clock Enable Control.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
Clock status monitor Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HXT_STB : HXT Clock Source Stable Flag
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
HXT clock is not stable or not enable
#1 : 1
HXT clock is stable
End of enumeration elements list.
LXT_STB : LXT Clock Source Stable Flag
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
LXT clock is not stable or not enable
#1 : 1
LXT clock is stable
End of enumeration elements list.
PLL_STB : PLL Clock Source Stable Flag
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
PLL clock is not stable or not enable
#1 : 1
PLL clock is stable
End of enumeration elements list.
LIRC_STB : LIRC Clock Source Stable Flag
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
LIRC clock is not stable or not enable
#1 : 1
LIRC clock is stable
End of enumeration elements list.
HIRC_STB : HIRC Clock Source Stable Flag
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
HIRC clock is not stable or not enable
#1 : 1
HIRC clock is stable
End of enumeration elements list.
CLK_SW_FAIL : Clock Switch Fail Flag\nThis bit will be set when target switch Clock Source is not stable. This bit is write 1 clear
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
Clock switch success
#1 : 1
Clock switch fail
End of enumeration elements list.
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