\n

DAC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x10 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected

Registers

DAC0_CTL

DAC1_CTL

DAC1_DATA

DAC1_STS

DAC01_COMCTL

DAC0_DATA

DAC0_STS


DAC0_CTL

DAC0 Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC0_CTL DAC0_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACEN DACIE DACLSEL DACPWONSTBCNT

DACEN : DAC Enable\nNote: When DAC is powered on, DAC will automatically start conversion after waiting for DACPWONSTBCNT+1 PCLK cycle.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Power down DAC

#1 : 1

Power on DAC

End of enumeration elements list.

DACIE : DAC Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

DACLSEL : DAC Load Selection
bits : 4 - 6 (3 bit)
access : read-write

DACPWONSTBCNT : DACPWONSTBCNT\nDAC need 6 us to be stable after DAC is power on from power down state.\nThis fied controls a internal counter (in PCLK unit) to guarantee DAC stable time requirement.
bits : 8 - 21 (14 bit)
access : read-write


DAC1_CTL

DAC1 Control Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC1_CTL DAC1_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAC1_DATA

DAC1 Data Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC1_DATA DAC1_DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAC1_STS

DAC1 Status Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC1_STS DAC1_STS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAC01_COMCTL

DAC01 Common Control Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC01_COMCTL DAC01_COMCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAITDACCONV DAC01GRP REFSEL

WAITDACCONV : Wait DAC Conversion Complete The DAC needs at least 2 us to settle down every time when each data deliver to DAC, which means user cannot update each DACx_data register faster than 2 us otherwise data will lost. Setting this register can adjust the time interval in PCLK unit between each DACx_data into DAC in order to meet the 2 us requirement.
bits : 0 - 7 (8 bit)
access : read-write

DAC01GRP : Group DAC0 and DAC1.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Not grouped

#1 : 1

Grouped

End of enumeration elements list.

REFSEL : Reference Voltage Selection
bits : 9 - 10 (2 bit)
access : read-write


DAC0_DATA

DAC0 Data Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC0_DATA DAC0_DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACData

DACData : DAC data
bits : 0 - 11 (12 bit)
access : read-write


DAC0_STS

DAC0 Status Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC0_STS DAC0_STS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACIFG DACSTFG BUSY

DACIFG : DAC Interrupt flag\nNote: This bit is read only.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt pending

#1 : 1

Interrupt pending

End of enumeration elements list.

DACSTFG : DAC start flag\nNote: this bit is read only.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

DAC is not start yet

#1 : 1

DAC has been started

End of enumeration elements list.

BUSY : BUSY bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

DAC is not busy

#1 : 1

DAC is busy

End of enumeration elements list.



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