VDMA_CSR (CSR)

VDMA_CSAR (CSAR)

VDMA_CDAR (CDAR)

VDMA_CBCR (CBCR)

VDMA_IER (IER)

VDMA_ISR (ISR)

VDMA_SASOCR (SASOCR)

VDMA_DASOCR (DASOCR)

VDMA_SAR (SAR)

VDMA_DAR (DAR)

VDMA_BUF0 (BUF0)

VDMA_BUF1 (BUF1)

VDMA_BCR (BCR)

VDMACEN : VDMA Channel Enable Setting this bit to 1 enables VDMA's operation. If this bit is cleared, VDMA will ignore all VDMA request and force Bus Master into IDLE state. Note: SW_RST will clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

SW_RST : Software Engine Reset
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STRIDE_EN : Stride Mode Enable
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIR_SEL : Transfer Source/Destination Address Direction Select
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRIG_EN : TRIG_EN\nNote1: When VDMA transfer is completed, this bit will be cleared automatically.\nNote2: If the bus error occurs, all VDMA transfer will be stopped. Software must reset all VDMA channel, and then trig again.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VDMA_CSAR : VDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the VDMA transfer is just occurring.
bits : 0 - 31 (32 bit)
access : read-only

VDMA_CDAR : VDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the VDMA transfer is just occurring.
bits : 0 - 31 (32 bit)
access : read-only

VDMA_CBCR : VDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of VDMA.
bits : 0 - 15 (16 bit)
access : read-only

TABORT_IE : VDMA Read/Write Target Abort Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TD_IE : VDMA Transfer Done Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TABORT_IS : VDMA Read/Write Target Abort Interrupt Status Flag Note1: This bit is cleared by writing 1 to itself. Note2: The VDMA_ISR [TABORT_IF] indicate bus master received ERROR response or not, if bus master received occur it means that target abort is happened. VDMA controller will stop transfer and respond this event to software then go to IDLE state. When target abort occurred, software must reset VDMA controller, and then transfer those data again.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TD_IS : Transfer Done Interrupt Status Flag This bit indicates that VDMA has finished all transfer. Note: This bit is cleared by writing 1 to itself.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SASTOBL : VDMA Source Address Stride Offset Byte Length\nThe 16-bit register defines the source address stride transfer offset count of each row.
bits : 0 - 15 (16 bit)
access : read-write

STBC : VDMA Stride Transfer Byte Count\nThe 16-bit register defines the stride transfer byte count of each row.
bits : 16 - 31 (16 bit)
access : read-write

DASTOBL : VDMA Destination Address Stride Offset Byte Length\nThe 16-bit register defines the destination address stride transfer offset count of each row.
bits : 0 - 15 (16 bit)
access : read-write

VDMA_SAR : VDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of VDMA.
bits : 0 - 31 (32 bit)
access : read-write

VDMA_DAR : VDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of VDMA.
bits : 0 - 31 (32 bit)
access : read-write

VDMA_BUF0 : VDMA Internal Buffer FIFO 0 (Read Only)\nVDMA channel has its own 2 words internal buffer.
bits : 0 - 31 (32 bit)
access : read-only

VDMA_BUF1 : VDMA Internal Buffer FIFO 1 (Read Only)\nVDMA channel has its own 2 words internal buffer.
bits : 0 - 31 (32 bit)
access : read-only

VDMA_BCR : VDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count of VDMA.
bits : 0 - 15 (16 bit)
access : read-write