PDMA_CSR4

PDMA_CSAR4

PDMA_CDAR4

PDMA_CBCR4

PDMA_IER4

PDMA_ISR4

PDMA_TCR4

PDMA_SAR4

PDMA_DAR4

PDMA_BUF4

PDMA_BCR4

PDMACEN : PDMA Channel Enable Setting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. Note: SW_RST will clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

SW_RST : Software Engine Reset
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE_SEL : PDMA Mode Select\n
bits : 2 - 3 (2 bit)
access : read-write

SAD_SEL : Transfer Source Address Direction Selection\n
bits : 4 - 5 (2 bit)
access : read-write

DAD_SEL : Transfer Destination Address Direction Selection\n
bits : 6 - 7 (2 bit)
access : read-write

TO_EN : Time-out Enable\nThis bit will enable PDMA internal Timer. While Timer is counted to zero, the TO_IS will be set.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

APB_TWS : Peripheral Transfer Width Selection
bits : 19 - 20 (2 bit)
access : read-write

TRIG_EN : TRIG_EN\nNote1: When PDMA transfer completed, this bit will be cleared automatically.\nNote2: If the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trig again.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMA_CSAR : PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer is just occurring.
bits : 0 - 31 (32 bit)
access : read-only

PDMA_CDAR : PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer is just occurring.
bits : 0 - 31 (32 bit)
access : read-only

PDMA_CBCR : PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: These fields will be changed when PDMA finish data transfer (data transfer to destination address),
bits : 0 - 23 (24 bit)
access : read-only

TABORT_IE : PDMA Read/Write Target Abort Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TD_IE : PDMA Transfer Done Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WRA_BCR_IE : Wrap Around Byte Count Interrupt Enable\n
bits : 2 - 5 (4 bit)
access : read-write

TO_IE : Time-Out Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TABORT_IS : PDMA Read/Write Target Abort Interrupt Status Flag Note1: This bit is cleared by writing 1 to itself. Note2: The PDMA_ISR [TABORT_IF] indicate bus master received ERROR response or not, if bus master received occur it means that target abort is happened. PDMA controller will stop transfer and respond this event to software then go to IDLE state. When target abort occurred, software must reset PDMA controller, and then transfer those data again.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TD_IS : Transfer Done Interrupt Status Flag This bit indicates that PDMA has finished all transfer. Note: This bit is cleared by writing 1 to itself.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WRA_BCR_IS : Wrap Around Transfer Byte Count Interrupt Status Flag
bits : 2 - 5 (4 bit)
access : read-write

TO_IS : Time-Out Interrupt Status Flag This flag indicated that PDMA has waited peripheral request for a period defined by PDMA_TCR. Note: This bit is cleared by writing 1 to itself.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMA_TCR : PDMA Timer Count Setting Register\nEach PDMA controller contains an internal counter. The internal counter starts counting when setting PDMA_CSRx [TO_EN] register, clearing and restart counting when complete each peripheral request service.
bits : 0 - 15 (16 bit)
access : read-write

PDMA_SAR : PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment.
bits : 0 - 31 (32 bit)
access : read-write

PDMA_DAR : PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote : The destination address must be word alignment
bits : 0 - 31 (32 bit)
access : read-write

PDMA_BUF : PDMA Internal Buffer FIFO (Read Only)\nEach channel has its own 1 words internal buffer.
bits : 0 - 31 (32 bit)
access : read-only

PDMA_BCR : PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count of PDMA.
bits : 0 - 15 (16 bit)
access : read-write