DMA_GCRCSR

DMA_DSSR0

DMA_DSSR1

DMA_GCRISR

CLK0_EN : DMA Controller Channel 0 Clock Enable Control
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLK1_EN : DMA Controller Channel 1 Clock Enable Control
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLK2_EN : DMA Controller Channel 2 Clock Enable Control
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLK3_EN : DMA Controller Channel 3 Clock Enable Control
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLK4_EN : DMA Controller Channel 4 Clock Enable Control
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLK5_EN : DMA Controller Channel 5 Clock Enable Control
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLK6_EN : DMA Controller Channel 6 Clock Enable Control
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRC_CLK_EN : CRC Controller Clock Enable Control
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH1_SEL : Channel 1 Selection
bits : 8 - 12 (5 bit)
access : read-write

CH2_SEL : Channel 2 Selection \nThis filed defines which peripheral is connected to PDMA channel 2. Software can configure the peripheral setting by CH2_SEL. The channel configuration is the same as CH1_SEL field. Please refer to the explanation of CH1_SEL.
bits : 16 - 20 (5 bit)
access : read-write

CH3_SEL : Channel 3 Selection \nThis filed defines which peripheral is connected to PDMA channel 3. Software can configure the peripheral setting by CH3_SEL. The channel configuration is the same as CH1_SEL field. Please refer to the explanation of CH1_SEL.
bits : 24 - 28 (5 bit)
access : read-write

CH4_SEL : Channel 4 Selection
bits : 0 - 4 (5 bit)
access : read-write

CH5_SEL : Channel 5 Selection \nThis filed defines which peripheral is connected to PDMA channel 5. Software can configure the peripheral setting by CH5_SEL. The channel configuration is the same as CH4_SEL field. Please refer to the explanation of CH4_SEL.
bits : 8 - 12 (5 bit)
access : read-write

CH6_SEL : Channel 6 Selection \nThis filed defines which peripheral is connected to PDMA channel 6. Software can configure the peripheral setting by CH6_SEL. The channel configuration is the same as CH4_SEL field. Please refer to the explanation of CH4_SEL.
bits : 16 - 20 (5 bit)
access : read-write

INTR0 : Interrupt Pin Status Of Channel 0 (Read Only)\nThis bit is the Interrupt pin status of DMA channel0.\nNote: This bit is read only
bits : 0 - 0 (1 bit)
access : read-only

INTR1 : Interrupt Pin Status Of Channel 1 (Read Only)\nThis bit is the Interrupt pin status of DMA channel1.\nNote: This bit is read only
bits : 1 - 1 (1 bit)
access : read-only

INTR2 : Interrupt Pin Status Of Channel 2 (Read Only)\nThis bit is the Interrupt pin status of DMA channel2.\nNote: This bit is read only
bits : 2 - 2 (1 bit)
access : read-only

INTR3 : Interrupt Pin Status Of Channel 3 (Read Only)\nThis bit is the Interrupt pin status of DMA channel3.\nNote: This bit is read only
bits : 3 - 3 (1 bit)
access : read-only

INTR4 : Interrupt Pin Status Of Channel 4 (Read Only)\nThis bit is the Interrupt pin status of DMA channel4.\nNote: This bit is read only
bits : 4 - 4 (1 bit)
access : read-only

INTR5 : Interrupt Pin Status Of Channel 5 (Read Only)\nThis bit is the Interrupt pin status of DMA channel4.\nNote: This bit is read only
bits : 5 - 5 (1 bit)
access : read-only

INTR6 : Interrupt Pin Status Of Channel 6 (Read Only)\nThis bit is the Interrupt pin status of DMA channel4.\nNote: This bit is read only
bits : 6 - 6 (1 bit)
access : read-only

CRC_INTR : Interrupt Pin Status of CRC Controller\nThis bit is the Interrupt status of CRC controller\nNote: This bit is read only
bits : 16 - 16 (1 bit)
access : read-only