ISPCON

ISPTRG

DFBADR

ISPADR

ISPSTA

ISPDAT

ISPCMD

ISPEN : ISP Enable (Erite-protection Bit)\nISP function enable bit. Set this bit to enable ISP function.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BS : Boot Select (Write-protection Bit) Set/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in Config0 after power-on reset It keeps the same value at other reset.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

APUEN : APROM Update Enable (Write-protection Bit)\nAPROM update enable bit.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFGUEN : Enable Config-bits Update by ISP (Write-protection Bit)
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LDUEN : LDROM Update Enable (Write-protection Bit)\nLDROM update enable bit.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPFF : ISP Fail Flag (Write-protection Bit)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself\n(2) LDROM writes to itself\n(3) CONFIG is erased/programmed if CFGUEN is set to 0\n(4) Destination address is illegal, such as over an available range\nWrite 1 to clear.
bits : 6 - 6 (1 bit)
access : read-write

PT : Flash Program Time (Write-protection Bits)
bits : 8 - 10 (3 bit)
access : read-write

ET : Flash Erase Time (Write-protection Bits)
bits : 12 - 14 (3 bit)
access : read-write

ISPGO : ISP Start Trigger\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DFBA : Data Flash Base Address\nThis register indicates data flash start address. It is a read only register.\nThe data flash start address is defined by user. Since on chip flash erase unit is 512 bytes, it is mandatory to keep bit 8-0 as 0.
bits : 0 - 31 (32 bit)
access : read-only

ISPADR : ISP Address\nThis chip supports word program only. ISPADR[1:0] must be kept 00b for ISP operation, and ISPADR[8:0] must be kept 0_0000_0000b for Vector Page Re-map Command
bits : 0 - 31 (32 bit)
access : read-write

ISPBUSY : ISP BUSY\nRead Only
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CBS : Config Boot Selection Status
bits : 1 - 2 (2 bit)
access : read-write

ISPFF : ISP Fail Flag\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself.\n(2) LDROM writes to itself. \n(3) CONFIG is erased/programmed when the MCU is running in APROM.\n(4) Destination address is illegal, such as over an available range.\nWrite 1 to clear.
bits : 6 - 6 (1 bit)
access : read-write

VECMAP : Vector Page Mapping Address The current flash address space 0x0000_0000~0x0000_01FF is mapping to address {VEC}AP[11:0], 000000000b } ~ {VEC}AP[11:0], 111111111b } Read Only
bits : 9 - 20 (12 bit)
access : read-write

ISPDAT : ISP Data\nWrite data to this register before ISP program operation\nRead data from this register after ISP read operation
bits : 0 - 31 (32 bit)
access : read-write

FCTRL : ISP Command\nThe ISP command table is shown as follows.
bits : 0 - 3 (4 bit)
access : read-write

FCEN : ISP Command\nThe ISP command table is shown as follows.
bits : 4 - 4 (1 bit)
access : read-write

FOEN : ISP Command\nThe ISP command table is shown as follows.
bits : 5 - 5 (1 bit)
access : read-write