I2CCON

I2CTOUT

I2CDATA

I2CSADDR0

I2CSADDR1

I2CSAMASK0

I2CSAMASK1

I2CWKUPCON

I2CINTSTS

I2CWKUPSTS

I2CSTATUS

I2CDIV

IPEN : I2C Function Enable\nWhen this bit is set to 1, the I2C serial function is enabled.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACK : Assert Acknowledge Control Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STOP : I2C STOP Control Bit. In Master mode, set this bit to 1 to transmit a STOP condition to bus then the controller will check the bus condition if a STOP condition is detected and this bit will be cleared by hardware automatically. In Slave mode, set this bit to 1 to reset the controller to the defined not addressed Slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

START : I2C START Command\nSetting this bit to 1 to enter Master mode, the device sends a START or repeat START condition to bus when the bus is free and it will be cleared to 0 after the START command is active and the STATUS has been updated.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C_STS : I2C Status. \nWhen a new state is present in the I2CSTATUS register, this bit will be set automatically, and if the INTEN bit is set, the I2C interrupt is requested. It must be cleared by software by writing one to this bit and the I2C protocol function will go ahead until the STOP is active or the IPEN is disabled
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTEN : Interrupt Enable.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TOUTEN : Time-out Counter Enable/Disable\nWhen set this bit to enable, the 14 bits time-out counter will start counting when STAINTSTS is cleared. Setting flag STAINTSTS to high or the falling edge of I2C clock or stop signal will reset counter and re-start up counting after STAINTSTS is cleared.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIV4 : Time-Out Counter Input Clock Divider by 4 \nWhen this bit is set enabled, the Time-Out period is prolonging 4 times.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATA : I2C Data Register The DATA contains a byte of serial data to be transmitted or a byte which has just been received. The user can read from or write to this 8-bit I2CDATA register directly while it is not in the process of shifting a byte. This occurs when the serial interrupt flag is set. Data in DATA remains stable as long as I2C_STS bit is set. While data is being shifted out, data on the bus is simultaneously being shifted in The DATA always contains the last data byte present on the bus. Thus, in the event of arbitration lost, the transition from master transmitter to slave receiver is made with the correct data in DATA. DATA and the acknowledge bit form a 9-bit shift register, the acknowledge bit is controlled by the device hardware and cannot be accessed by the user. Serial data is shifted through the acknowledge bit into DATA on the rising edges of serial clock pulses on the SCL line. When a byte has been shifted into DATA, the serial data is available in DATA, and the acknowledge bit (ACK or NACK) is returned by the control logic during the ninth clock pulse.
bits : 0 - 7 (8 bit)
access : read-write

GCALL : General Call Function The I2C controller supports the General Call function. If the GCALL bit is set, the controller will respond to General Call address (00H). When GCALL bit is set, the controller is in Slave mode, it can receive the general call address by 00H after Master send general call address to the I2C bus, then it will follow status of GCALL mode. If it is in Master mode, the ACK bit must be cleared when it will send general call address of 00H to I2C bus.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SADDR : I2C Salve Address Register\nThe content of this register is irrelevant when the device is in Master mode. In the Slave mode, the seven most significant bits must be loaded with the device's own address. The device will react if either of the address is matched.
bits : 1 - 7 (7 bit)
access : read-write

WKUPEN : I2C Wake-up Function Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SAMASK : I2C Slave Address Mask Register\nI2C bus controllers support multiple address recognition with two address mask registers. When the bit in the address mask register is set to b'1, it means the received corresponding address bit is don't-care. If the bit is set to b'0, that means the received corresponding register bit should be exact the same as address register.
bits : 1 - 7 (7 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKUPEN : I2C Wake-up Function Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSTS : I2S STATUS's Interrupt Status\nWhen a new state is present in the I2CSTATUS register, this bit will be set automatically, and if INTEN bit is set, the I2C interrupt is requested. Software can write one to cleat this bit.
bits : 0 - 0 (1 bit)
access : read-write

TIF : Time-out Status
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKUPIF : Wake-up Interrupt Flag\nSoftware can write one to clear this flag
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

STATUS : I2C Status Register\nIn addition, states 00H stands for a 'Bus Error'. A 'Bus Error' occurs when a START or STOP condition is present at an illegal position in the formation frame. Example of illegal position: a data byte or an acknowledge bit is present during the serial transfer of an address byte. \nTo recover I2C from bus error, STOP should be set and I2C_STS should be cleared to enter not addressed Slave mode. Then clear STOP to release the bus and to wait new communication. I2C bus can not recognize stop condition during this action when bus error occurs.
bits : 0 - 7 (8 bit)
access : read-only

CLK_DIV : I2C Clock Divider
bits : 0 - 7 (8 bit)
access : read-write