PWM_PRES

PWM_INTSTS

PWM_OE

PWM_DUTY0

PWM_DATA0

PWM_DUTY1

PWM_DATA1

PWM_DUTY2

PWM_DATA2

PWM_CLKSEL

PWM_DUTY3

PWM_DATA3

PWM_CAPCTL

PWM_CAPINTEN

PWM_CAPINTSTS

PWM_CRL0

PWM_CFL0

PWM_CRL1

PWM_CFL1

PWM_CRL2

PWM_CFL2

PWM_CRL3

PWM_CFL3

PWM_CTL

PWM_PDMACH0

PWM_PDMACH2

PWM_INTEN

CP01 : Clock Prescaler 0 for PWM Timer 0 1 Clock input is divided by (CP01 + 1) before it is fed to the counter 0 1
bits : 0 - 7 (8 bit)
access : read-write

CP23 : Clock Prescaler 2 for PWM Timer 2 3 Clock input is divided by (CP23 + 1) before it is fed to the counter 2 3
bits : 8 - 15 (8 bit)
access : read-write

DZ01 : Dead Zone Interval Register for CH0 and CH1 Pair\nThese 8 bits determine dead zone length.\nThe unit time of dead zone length is received from clock selector 0.
bits : 16 - 23 (8 bit)
access : read-write

DZ23 : Dead Zone Interval Register for CH2 and CH3 Pair\nThese 8 bits determine dead zone length.\nThe unit time of dead zone length is received from clock selector 2.
bits : 24 - 31 (8 bit)
access : read-write

TMINT0 : PWM Timer 0 Interrupt Flag\nFlag is set by hardware when PWM0 down counter reaches zero, software can clear this bit by writing a one to it.
bits : 0 - 0 (1 bit)
access : read-write

TMINT1 : PWM Timer 1 Interrupt Flag\nFlag is set by hardware when PWM1 down counter reaches zero, software can clear this bit by writing a one to it.
bits : 1 - 1 (1 bit)
access : read-write

TMINT2 : PWM Timer 2 Interrupt Flag\nFlag is set by hardware when PWM2 down counter reaches zero, software can clear this bit by writing a one to it.
bits : 2 - 2 (1 bit)
access : read-write

TMINT3 : PWM Timer 3 Interrupt Flag\nFlag is set by hardware when PWM3 down counter reaches zero, software can clear this bit by writing a one to it.
bits : 3 - 3 (1 bit)
access : read-write

Duty0Syncflag : Duty0 Synchronize Flag\nNote: software should check this flag when writing duty0, if this flag is set, and user ignore this flag and change duty0, the corresponding CNR and CMR may be wrong for one duty cycle
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

Duty1Syncflag : Duty1 Synchronize Flag\nNote: software should check this flag when writing duty1, if this flag is set, and user ignore this flag and change duty1, the corresponding CNR and CMR may be wrong for one duty cycle
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

Duty2Syncflag : Duty2 Synchronize Flag\nNote: software should check this flag when writing duty2, if this flag is set, and user ignore this flag and change duty2, the corresponding CNR and CMR may be wrong for one duty cycle
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

Duty3Syncflag : Duty3 Synchronize Flag\nNote: software should check this flag when writing duty3, if this flag is set, and user ignore this flag and change duty3, the corresponding CNR and CMR may be wrong for one duty cycle
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PresSyncFlag : Prescale Synchronize Flag Note: software should check this flag when writing Prescale, if this flag is set, and user ignore this flag and change Prescale, the Prescale may be wrong for one prescale cycle
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH0_OE : PWM CH0 Output Enable Register\nNote: The corresponding GPI/O pin also must be switched to PWM function (refer to GPx_MFP)
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH1_OE : PWM CH1 Output Enable Register\nNote: The corresponding GPI/O pin also must be switched to PWM function (refer to GPx_MFP)
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH2_OE : PWM CH2 Output Enable Register\nNote: The corresponding GPI/O pin also must be switched to PWM function (refer to GPx_MFP)
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH3_OE : PWM CH3 Output Enable Register\nNote: The corresponding GPI/O pin also must be switched to PWM function (refer to GPx_MFP)
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CN : PWM Counter/Timer Loaded Value\nCN determines the PWM period.\nNote: \nAny write to CN will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write

CM : PWM Comparator Register\nCM determines the PWM duty.\nNote:\n Any write to CM will take effect in next PWM cycle.
bits : 16 - 31 (16 bit)
access : read-write

PWMx_DATAy15_0 : PWM Data Register\nUser can monitor PWMx_DATAy to know the current value in 16-bit down count counter.
bits : 0 - 15 (16 bit)
access : read-only

PWMx_DATAy30_16 : PWM Data Register \nUser can monitor PWMx_DATAy to know the current value in 32-bit down count counter\nNotes:This will be valid only for the corresponding cascade enable .bit is set
bits : 16 - 30 (15 bit)
access : read-only

sync : Indicate that CNR value is sync to PWM counter\nNote: when the corresponding cascade enable .bit is set is bit will not appear in the corresponding channel
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CLKSEL0 : Timer 0 Clock Source Selection\nSelect clock input for timer 0.\n(Table is the same as CLKSEL3)
bits : 0 - 2 (3 bit)
access : read-write

CLKSEL1 : Timer 1 Clock Source Selection\nSelect clock input for timer 1.\n(Table is the same as CLKSEL3)
bits : 4 - 6 (3 bit)
access : read-write

CLKSEL2 : Timer 2Clock Source Selection\nSelect clock input for timer 2.\n(Table is the same as CLKSEL3)
bits : 8 - 10 (3 bit)
access : read-write

CLKSEL3 : Timer 3 Clock Source Selection
bits : 12 - 14 (3 bit)
access : read-write

INV0 : Channel 0 Inverter ON/OFF
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPCH0EN : Capture Channel 0 transition Enable/Disable\nWhen Enabled, Capture latched the PWM-timer value and saved to PWM_CRL0 (Rising latch) and PWM_CFL0 (Falling latch).\nWhen Disabled, Capture does not update PWM_CRL0 and PWM_CFL0, and disable Channel 0 Interrupt.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPCH0PADEN : Capture Input Enable Register
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH0PDMAEN : Channel 0 PDMA Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMACAPMOD0 : Select CRL0 or CFL0 for PDMA Transfer
bits : 4 - 5 (2 bit)
access : read-write

CAPRELOADREN0 : Reload CNR0 when CH0 Capture Rising Event Comes
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPRELOADFEN0 : Reload CNR0 when CH0 Capture Falling Event Comes
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INV1 : Channel 1 Inverter ON/OFF
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPCH1EN : Capture Channel 1 transition Enable/Disable\nWhen Enabled, Capture latched the PMW-counter and saved to PWM_CRL1 (Rising latch) and PWM_CFL1 (Falling latch).\nWhen Disabled, Capture does not update PWM_CRL1 and PWM_CFL1, and disable Channel 1 Interrupt.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPCH1PADEN : Capture Input Enable Register
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH0RFORDER : None
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH01CASK : Cascade channel 0 and channel 1 PWM timer for capturing usage
bits : 13 - 13 (1 bit)
access : read-write

CAPRELOADREN1 : Reload CNR1 when CH1 Capture Rising Event Comes
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPRELOADFEN1 : Reload CNR1 when CH1 capture falling event coming
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INV2 : Channel 2 Inverter ON/OFF
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPCH2EN : Capture Channel 2 transition Enable/Disable\nWhen Enabled, Capture latched the PWM-timer value and saved to PWM_CRL2 (Rising latch) and PWM_CFL2 (Falling latch).\nWhen Disabled, Capture does not update PWM_CRL2 and PWM_CFL2, and disable Channel 2 Interrupt.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPCH2PADEN : Capture Input Enable Register
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH2PDMAEN : Channel 2 PDMA Enable
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMACAPMOD2 : Select CRL2 or CFL2 for PDMA Transfer
bits : 20 - 21 (2 bit)
access : read-write

CAPRELOADREN2 : Reload CNR2 when CH2 capture rising event coming
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPRELOADFEN2 : Reload CNR2 when CH2 capture failing event coming
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INV3 : Channel 3 Inverter ON/OFF
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPCH3EN : Capture Channel 3 transition Enable/Disable\nWhen Enabled, Capture latched the PMW-timer and saved to PWM_CRL3 (Rising latch) and PWM_CFL3 (Falling latch).\nWhen Disabled, Capture does not update PWM_CRL3 and PWM_CFL3, and disable Channel 3 Interrupt.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPCH3PADEN : Capture Input Enable Register
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH2RFORDER : None
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH23CASK : Cascade channel 2 and channel 3 PWM counter for capturing usage
bits : 29 - 29 (1 bit)
access : read-write

CAPRELOADREN3 : Reload CNR3 when CH3 Rising Capture Event Comes
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPRELOADFEN3 : Reload CNR3 when CH3 falling capture Event Comes
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRL_IE0 : Channel 0 Rising Latch Interrupt Enable ON/OFF\nWhen Enabled, if Capture detects Channel 0 has rising transition, Capture issues an Interrupt.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFL_IE0 : Channel 0 Falling Latch Interrupt Enable ON/OFF\nWhen Enabled, if Capture detects Channel 0 has falling transition, Capture issues an Interrupt.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRL_IE1 : Channel 1 Rising Latch Interrupt Enable \nWhen Enabled, if Capture detects Channel 1 has rising transition, Capture issues an Interrupt.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFL_IE1 : Channel 1 Falling Latch Interrupt Enable \nWhen Enabled, if Capture detects Channel 1 has falling transition, Capture issues an Interrupt.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRL_IE2 : Channel 2 Rising Latch Interrupt Enable ON/OFF\nWhen Enabled, if Capture detects Channel 2 has rising transition, Capture issues an Interrupt.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFL_IE2 : Channel 2 Falling Latch Interrupt Enable ON/OFF\nWhen Enabled, if Capture detects Channel 2 has falling transition, Capture issues an Interrupt.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRL_IE3 : Channel 3 Rising Latch Interrupt Enable ON/OFF\nWhen Enabled, if Capture detects Channel 3 has rising transition, Capture issues an Interrupt.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFL_IE3 : Channel 3 Falling Latch Interrupt Enable ON/OFF\nWhen Enabled, if Capture detects Channel 3 has falling transition, Capture issues an Interrupt.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPIF0 : Capture0 Interrupt Indication Flag
bits : 0 - 0 (1 bit)
access : read-write

CRLI0 : PWM_CRL0 Latched Indicator Bit\nWhen input channel 0 has a rising transition, PWM0_CRL0 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write

CFLRI0 : PWM_CFL0 Latched Indicator Bit\nWhen input channel 0 has a falling transition, PWM0_CFL0 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
bits : 2 - 2 (1 bit)
access : read-write

CAPOVR0 : Capture Rising Flag Over Run for Channel 0\nThis flag indicate CRL0 update faster than software reading it when it is set \nThis bit will be cleared automatically when user clears CRLI0 bit 1 of PWM_CAPINTSTS.
bits : 3 - 3 (1 bit)
access : read-write

CAPOVF0 : Capture Falling Flag Over Run for Channel 0\nThis flag indicate CFL0 update faster than software reading it when it is set.
bits : 4 - 4 (1 bit)
access : read-write

CAPIF1 : Capture1 Interrupt Indication Flag
bits : 8 - 8 (1 bit)
access : read-write

CRLI1 : PWM_CRL1 Latched Indicator Bit\nWhen input channel 1 has a rising transition, PWM0_CRL1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
bits : 9 - 9 (1 bit)
access : read-write

CFLI1 : PWM_CFL1 Latched Indicator Bit\nWhen input channel 1 has a falling transition, PWM0_CFL1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
bits : 10 - 10 (1 bit)
access : read-write

CAPOVR1 : Capture Rising Flag Over Run for Channel 1\nThis flag indicate CRL1 update faster than software reading it when it is set \nThis bit will be cleared automatically when user clear CRLI1 bit 9 of PWM_CAPINTSTS
bits : 11 - 11 (1 bit)
access : read-write

CAPOVF1 : Capture Falling Flag Over Run for Channel 1\nThis flag indicate CFL1 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CFLI1 bit 10 of PWM_CAPINTSTS
bits : 12 - 12 (1 bit)
access : read-write

CAPIF2 : Capture2 Interrupt Indication Flag
bits : 16 - 16 (1 bit)
access : read-write

CRLI2 : PWM_CRL2 Latched Indicator Bit\nWhen input channel 2 has a rising transition, PWM0_CRL2 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
bits : 17 - 17 (1 bit)
access : read-write

CFLI2 : PWM_CFL2 Latched Indicator Bit\nWhen input channel 2 has a falling transition, PWM0_CFL2 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
bits : 18 - 18 (1 bit)
access : read-write

CAPOVR2 : Capture Rising Flag Over Run for Channel 2\nThis flag indicate CRL2 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CRLI2 bit 17 of PWM_CAPINTSTS
bits : 19 - 19 (1 bit)
access : read-write

CAPOVF2 : Capture Falling Flag Over Run for Channel 2 \nThis flag indicate CFL2 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CFLI2 bit 18 of PWM_CAPINTSTS
bits : 20 - 20 (1 bit)
access : read-write

CAPIF3 : Capture3 Interrupt Indication Flag
bits : 24 - 24 (1 bit)
access : read-write

CRLI3 : PWM_CRL3 Latched Indicator Bit\nWhen input channel 3 has a rising transition, PWM_CRL3 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
bits : 25 - 25 (1 bit)
access : read-write

CFLI3 : PWM_CFL3 Latched Indicator Bit\nWhen input channel 3 has a falling transition, PWM_CFL3 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
bits : 26 - 26 (1 bit)
access : read-write

CAPOVR3 : Capture Rising Flag Over Run for Channel 3\nThis flag indicate CRL3update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CRLI3 bit 25 of PWM_CAPINTSTS
bits : 27 - 27 (1 bit)
access : read-write

CAPOVF3 : Capture Falling Flag Over Run for Channel 3 \nThis flag indicate CFL3 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CFLI3 bit 26 of PWM_CAPINTSTS
bits : 28 - 28 (1 bit)
access : read-write

CRL15_0 : Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition.
bits : 0 - 15 (16 bit)
access : read-only

CRL31_16 : Upper Half Word of 32-bit Capture Data when Cascade Enabled\nWhen cascade is enabled for capture channel 0, 2,the original 16 bit counter extend to 32 bit, and capture result CRL0 and CRL2 are also extend to 32 bit,
bits : 16 - 31 (16 bit)
access : read-only

CFL15_0 : Capture Falling Latch Register\nLatch the PWM counter when Channel 01/2/3 has Falling transition.
bits : 0 - 15 (16 bit)
access : read-only

CFL31_16 : Upper Half Word of 32-bit Capture Data When Cascade Enabled\nWhen cascade is enabled for capture channel 0, 2, the original 16 bit counter extend to 32 bit, and capture result CFL0 and CFL2 are also extend to 32 bit,
bits : 16 - 31 (16 bit)
access : read-only

CH0EN : PWM-Timer 0 Enable/Disable Start Run
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH0INV : PWM-Timer 0 Output Inverter ON/OFF
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH0MOD : PWM-Timer 0 Continuous/One-Shot Mode\nNote: If there is a rising transition at this bit, it will cause CN and CM of PWM0_DUTY0 to be cleared.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DZEN01 : Dead-Zone 0 Generator Enable/Disable\nNote: When Dead-Zone Generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DZEN23 : Dead-Zone 2 Generator Enable/Disable\nNote: When Dead-Zone Generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH1EN : PWM-Timer 1 Enable/Disable Start Run
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH1INV : PWM-Timer 1 Output Inverter ON/OFF
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH1MOD : PWM-Timer 1 Continuous/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause CN and CM of PWM0_DUTY1 to be cleared.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH2EN : PWM-Timer 2 Enable/Disable Start Run
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH2INV : PWM-Timer 2 Output Inverter ON/OFF
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH2MOD : PWM-Timer 2 Continuous/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause CN and CM of PWM0_DUTY2 be cleared.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH3EN : PWM-Timer 3 Enable/Disable Start Run
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH3INV : PWM-Timer 3 Output Inverter ON/OFF
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH3MOD : PWM-Timer 3 Continuous/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause CN and CM of PWM0_DUTY3 to be cleared.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

Captureddata7_0 : PDMACH0\nWhen CH01CASK is disabled, it is the capturing value(CFL0/CRL0) for channel 0\nWhen CH01CASK is enabled, It is the for the first byte of 32 bit capturing data for channel 0
bits : 0 - 7 (8 bit)
access : read-only

Captureddata15_8 : PDMACH0\nWhen CH01CASK is disabled, it is the capturing value(CFL0/CRL0) for channel 0\nWhen CH01CASK is enabled, It is the second byte of 32 bit capturing data for channel 0
bits : 8 - 15 (8 bit)
access : read-only

Captureddata23_16 : PDMACH0\nWhen CH01CASK is disabled, this byte is 0\nWhen CH01CASK is enabled, It is the third byte of 32 bit capturing data for channel 0
bits : 16 - 23 (8 bit)
access : read-only

Captureddata31_24 : PDMACH0\nWhen CH01CASK is disabled, this byte is 0\nWhen CH01CASK is enabled, It is the 4th byte of 32 bit capturing data for channel 0
bits : 24 - 31 (8 bit)
access : read-only

Captureddata7_0 : PDMACH0\nWhen CH23CASK is disabled, it is the capturing value(CFL0/CRL0) for channel 2\nWhen CH23CASK is enabled, It is the for the first byte of 32 bit capturing data for channel 2
bits : 0 - 7 (8 bit)
access : read-only

Captureddata15_8 : PDMACH0\nWhen CH23CASK is disabled, it is the capturing value(CFL0/CRL0) for channel 2\nWhen CH23CASK is enabled, It is the second byte of 32 bit capturing data for channel 2
bits : 8 - 15 (8 bit)
access : read-only

Captureddata23_16 : PDMACH0\nWhen CH23CASK is disabled, this byte is 0\nWhen CH23CASK is enabled, It is the third byte of 32 bit capturing data for channel 2
bits : 16 - 23 (8 bit)
access : read-only

Captureddata31_24 : PDMACH0\nWhen CH23CASK is disabled, this byte is 0\nWhen CH23CASK is enabled, It is the 4th byte of 32 bit capturing data for channel 2
bits : 24 - 31 (8 bit)
access : read-only

TMIE0 : PWM Timer 0 Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMIE1 : PWM Timer 1 Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMIE2 : PWM Timer 2 Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMIE3 : PWM Timer 3 Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.