SC_RBR

SC_THR

SC_RFTMR

SC_ETUCR

SC_IER

SC_ISR

SC_TRSR

SC_PINCSR

SC_TMR0

SC_TMR1

SC_TMR2

SC_UACTL

SC_TDRA

SC_TDRB

SC_CTL

SC_ALTCTL

SC_EGTR

RBR : Receive Buffer Register\nBy reading this register, the SC will return an 8-bit received data.
bits : 0 - 7 (8 bit)
access : read-only

THR : Transmit Holding Register\nBy writing to this register, the SC will send out an 8-bit data.\nNote: If SC_CTL [SC_CEN] not enabled, this register can not be programmed.
bits : 0 - 7 (8 bit)
access : write-only

RFTM : SC Receiver Buffer Time-Out Register (ETU Based) The time-out counter resets and starts counting whenever the RX buffer received a new data word. Once the counter decrease to 1 and no new data is received or CPU does not read data by reading SC_RBR register, a receiver time-out interrupt INT_RTMR will be generated(if SC_IER[RTMR_IE] is high). Note1: The counter is ETU based and the real count value is RFTM + 1 Note2: Fill all 0 to this field to disable this function.
bits : 0 - 8 (9 bit)
access : read-write

ETU_RDIV : ETU Rate Divider\nThe field indicates the clock rate divider.\nThe real ETU is ETU_RDIV + 1.\nNote1: Software can configure this field, but this field must be greater than 0x04.\nNote2: Software can configure this field, but if the error rate is equal to 2%, this field must be greater than 0x040.
bits : 0 - 11 (12 bit)
access : read-write

COMPEN_EN : Compensation Mode Enable\nThis bit enables clock compensation function. When this bit enabled, hardware will alternate between n clock cycles and (n-1) clock cycles, where n is the value to be written into the ETU_RDIV register.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RDA_IE : Receive Data Reach Interrupt Enable\nThis field is used for received data reaching trigger level (SC_CTL [RX_FTRI_LEV]) interrupt enable.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TBE_IE : Transmit Buffer Empty Interrupt Enable\nThis field is used for transmit buffer empty interrupt enable.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TERR_IE : Transfer Error Interrupt Enable This field is used for transfer error interrupt enable. The transfer error states is at SC_TRSR register which includes receiver break error (RX_EBR_F), frame error (RX_EFR_F), parity error (RX_EPA_F), receiver buffer overflow error (RX_OVER_F), transmit buffer overflow error (TX_OVER_F), receiver retry over limit error (RX_OVER_ERETRY) and transmitter retry over limit error (TX_OVER_ERETRY).
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0_IE : Timer0 Interrupt Enable\nThis field is used for TMR0 interrupt enable.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1_IE : Timer1 Interrupt Enable\nThis field is used for TMR1 interrupt enable.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR2_IE : Timer2 Interrupt Enable\nThis field is used for TMR2 interrupt enable.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BGT_IE : Block Guard Time Interrupt Enable\nThis field is used for block guard time interrupt enable.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CD_IE : Card Detect Interrupt Enable\nThis field is used for card detect interrupt enable. The card detect status register is SC_PINCSR [CD_CH] and SC_PINCSR[CD_CL].
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INIT_IE : Initial End Interrupt Enable\nThis field is used for activation (SC_ALTCTL [ACT_EN]), deactivation (SC_ALTCTL [DACT_EN]) and warm reset (SC_ALTCTL [WARST_EN]) sequence interrupt enable.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTMR_IE : Receiver Buffer Time-Out Interrupt Enable \nThis field is used for receiver buffer time-out interrupt enable.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACON_ERR_IE : Auto convention Error Interrupt Enable \nThis field is used for auto convention error interrupt enable.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

COMPEN_EN : Compensation Mode Enable\nThis bit enables clock compensation function. When this bit enabled, hardware will alternate between n clock cycles and (n-1) clock cycles, where n is the value to be written into the ETU_RDIV register.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RDA_IS : Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level (SC_CTL [RX_FTRI_LEV]) interrupt status flag.\nNote: This field is the status flag of received data reaching SC_CTL [RX_FTRI_LEV]. If software reads data from SC_RBR and receiver pointer is less than SC_CTL [RX_FTRI_LEV], this bit will be cleared automatically.
bits : 0 - 0 (1 bit)
access : read-only

TBE_IS : Transmit Buffer Empty Interrupt Status Flag (Read Only) This field is used for transmit buffer empty interrupt status flag. This bit is different with SC_TRSR [TX_EMPTY_F] flag and SC_TRSR [TX_ATV] flag The TX_EMPTY_F will be set when the last byte data be read to shift register and TX_ATV flag indicates the transmitter is in active or not (the last data has been transmitted or not), but the TBE_IS may be set when the last byte data be read to shift register or the last data has been transmitted. When this bit assert, software can write 1~4 byte data to SC_THR register. Note: If software wants to clear this bit, software must write data to SC_THR register and then this bit will be cleared automatically.
bits : 1 - 1 (1 bit)
access : read-only

TERR_IS : Transfer Error Interrupt Status Flag (Read Only) This field is used for transfer error interrupt status flag. The transfer error states is at SC_TRSR register which includes receiver break error (RX_EBR_F), frame error (RX_EFR_F), parity error (RX_EPA_F) and receiver buffer overflow error (RX_OVER_F), transmit buffer overflow error (TX_OVER_F), receiver retry over limit error (RX_OVER_ERETRY) and transmitter retry over limit error (TX_OVER_ERETRY). Note: This field is the status flag of SC_TRSR [RX_EBR_F], SC_TRSR [RX_EFR_F], SC_TRSR [RX_EPA_F], SC_TRSR [RX_OVER_F], SC_TRSR [TX_OVER_F], SC_TRSR [RX_OVER_ERETRY] or SC_TRSR [TX_OVER_ERETRY]. So if software wants to clear this bit, software must write 1 to each field.
bits : 2 - 2 (1 bit)
access : read-only

TMR0_IS : Timer0 Interrupt Status Flag (Read Only) This field is used for TMR0 interrupt status flag. Note: This bit is read only, but it can be cleared by writing 1 to it.
bits : 3 - 3 (1 bit)
access : read-only

TMR1_IS : Timer1 Interrupt Status Flag (Read Only) This field is used for TMR1 interrupt status flag. Note: This bit is read only, but it can be cleared by writing 1 to it.
bits : 4 - 4 (1 bit)
access : read-only

TMR2_IS : Timer2 Interrupt Status Flag (Read Only) This field is used for TMR2 interrupt status flag. Note: This bit is read only, but it can be cleared by writing 1 to it.
bits : 5 - 5 (1 bit)
access : read-only

BGT_IS : Block Guard Time Interrupt Status Flag (Read Only) This field is used for block guard time interrupt status flag. Note: This bit is read only, but it can be cleared by writing 1 to it.
bits : 6 - 6 (1 bit)
access : read-only

CD_IS : Card Detect Interrupt Status Flag (Read Only) This field is used for card detect interrupt status flag. The card detect status register is SC_PINCSR [CD_INS_F] and SC_PINCSR [CD_REM_F]. Note: This field is the status flag of SC_PINCSR [CD_INS_F] or SC_PINCSR [CD_REM_F]. So if software wants to clear this bit, software must write 1 to this field.
bits : 7 - 7 (1 bit)
access : read-only

INIT_IS : Initial End Interrupt Status Flag (Read Only) This field is used for activation (SC_ALTCTL [ACT_EN]), deactivation (SC_ALTCTL [DACT_EN]) and warm reset (SC_ALTCTL [WARST_EN]) sequence interrupt status flag. Note: This bit is read only, but it can be cleared by writing 1 to it.
bits : 8 - 8 (1 bit)
access : read-only

RTMR_IS : Receiver buffer Time-Out Interrupt Status Flag (Read Only)\nThis field is used for receiver buffer time-out interrupt status flag.\nNote: This field is the status flag of receiver buffer time-out state. If software wants to clear this bit, software must read the receiver buffer remaining data by reading SC_RBR register,
bits : 9 - 9 (1 bit)
access : read-only

ACON_ERR_IS : Auto Convention Error Interrupt Status Flag (Read Only) This field indicates auto convention sequence error. If the received TS at ATR state is not 0x3B or 0x3F, this bit will be set. Note: This bit is read only, but can be cleared by writing 1 to it.
bits : 10 - 10 (1 bit)
access : read-only

RX_OVER_F : RX Overflow Error Status Flag (Read Only) This bit is set when RX buffer overflow. If the number of received bytes is greater than RX Buffer (SC_RBR) size, 4 bytes of SC, this bit will be set. Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: The overwrite data will be ignored.
bits : 0 - 0 (1 bit)
access : read-only

RX_EMPTY_F : Receiver Buffer Empty Status Flag(Read Only)\nThis bit indicates RX buffer empty or not.\nWhen the last byte of RX buffer has been read by CPU, hardware sets this bit high. It will be cleared when SC receives any new data.
bits : 1 - 1 (1 bit)
access : read-only

RX_FULL_F : Receiver Buffer Full Status Flag (Read Only)\nThis bit indicates RX buffer full or not.\nThis bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
bits : 2 - 2 (1 bit)
access : read-only

RX_EPA_F : Receiver Parity Error Status Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid parity bit . Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: If CPU sets receiver retries function by setting SC_CTL [RX_ERETRY_EN] register, hardware will not set this flag.
bits : 4 - 4 (1 bit)
access : read-only

RX_EFR_F : Receiver Frame Error Status Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0 ). Note1: This bit is read only, but can be cleared by writing 1 to it. Note2: If CPI sets receiver retries function by setting SC_CTL [RX_ERETRY_EN] register, hardware will not set this flag.
bits : 5 - 5 (1 bit)
access : read-only

RX_EBR_F : Receiver Break Error Status Flag (Read Only) This bit is set to a logic 1 whenever the received data input (RX) held in the spacing state (logic 0 ) is longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). . Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: If CPU sets receiver retries function by setting SC_CTL [RX_ERETRY_EN] register, hardware will not set this flag.
bits : 6 - 6 (1 bit)
access : read-only

TX_OVER_F : TX Overflow Error Interrupt Status Flag (Read Only) Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: The additional write data will be ignored.
bits : 8 - 8 (1 bit)
access : read-only

TX_EMPTY_F : Transmit buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nWhen the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into SC_THR (TX buffer not empty).
bits : 9 - 9 (1 bit)
access : read-only

TX_FULL_F : Transmit buffer Full Status flag (Read Only)\nThis bit indicates TX buffer full or not.\nThis bit is set when TX pointer is equal to 4, otherwise is cleared by hardware.
bits : 10 - 10 (1 bit)
access : read-only

RX_POINT_F : Receiver Buffer Pointer Status Flag (Read Only)\nThis field indicates the RX buffer pointer status flag. When SC receives one byte from external device, RX_POINT_F increases one. When one byte of RX buffer is read by CPU, RX_POINT_F decreases one.
bits : 16 - 18 (3 bit)
access : read-only

RX_ERETRY_F : Receiver Retry Error (Read Only) This bit is set by hardware when RX has any error and retries transfer. Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2 This bit is a flag and can not generate any interrupt to CPU. Note3: If CPU enables receiver retry function by setting SC_CTL [RX_ERETRY_EN] register, the RX_EPA_F flag will be ignored (hardware will not set RX_EPA_F).
bits : 21 - 21 (1 bit)
access : read-only

RX_OVER_ERETRY : Receiver Over Retry Error (Read Only) This bit is set by hardware when RX transfer error retry over retry number limit. Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: If CPU enables receiver retries function by setting SC_CTL [RX_ERETRY_EN] register, the RX_EPA_F flag will be ignored (hardware will not set RX_EPA_F).
bits : 22 - 22 (1 bit)
access : read-only

RX_ATV : Receiver In Active Status Flag (Read Only)\nThis bit is set by hardware when RX transfer is in active.\nThis bit is cleared automatically when RX transfer is finished.
bits : 23 - 23 (1 bit)
access : read-only

TX_POINT_F : Transmit Buffer Pointer Status Flag (Read Only)\nThis field indicates the TX buffer pointer status flag. When CPU writes data into SC_THR, TX_POINT_F increases one. When one byte of TX Buffer is transferred to transmitter shift register, TX_POINT_F decreases one.
bits : 24 - 26 (3 bit)
access : read-only

TX_ERETRY_F : Transmitter Retry Error (Read Only) This bit is set by hardware when transmitter re-transmits. Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2 This bit is a flag and can not generate any interrupt to CPU.
bits : 29 - 29 (1 bit)
access : read-only

TX_OVER_ERETRY : Transmitter Over Retry Error (Read Only) This bit is set by hardware when transmitter re-transmits over retry number limitation. Note: This bit is read only, but it can be cleared by writing 1 to it.
bits : 30 - 30 (1 bit)
access : read-only

TX_ATV : Transmit In Active Status Flag (Read Only)\nThis bit is set by hardware when TX transfer is in active or the last byte transmission has not completed.\nThis bit is cleared automatically when TX transfer is finished and the STOP bit (include guard time) has been transmitted.
bits : 31 - 31 (1 bit)
access : read-only

POW_EN : SC_POW_EN Pin Signal\nThis bit is the pin status of SC_POW_EN but user can drive SC_POW_EN pin to high or low by setting this bit.\nNote: When operation at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field When operating in these modes.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SC_RST : SC_RST Pin Signal\nThis bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit.\nNote: When operation at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field When operating in these modes.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CD_REM_F : Card Detect Removal Status Of SC_CD Pin (Read Only) This bit is set whenever card has been removal. Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: Card detect engine will start after SC_CTL [SC_CEN] set.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CD_INS_F : Card Detect Insert Status Of SC_CD Pin (Read Only) This bit is set whenever card has been inserted. Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: Card detect engine will start after SC_CTL [SC_CEN] set.
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CD_PIN_ST : Card Detect Status Of SC_CD Pin Status (Read Only)\nThis bit is the pin status flag of SC_CD
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CLK_STOP_LEV : SC Clock Stop Level\nThis field indicates the clock polarity control in clock stop mode.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLK_KEEP : SC Clock Enable \nNote: When operation at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field When operating in these modes.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADAC_CD_EN : Auto Deactivation When Card Removal\nNote1: When the card is removal, hardware will stop any process and then do deactivation sequence (if this bit be setting). If this process completes. Hardware will generate an interrupt INT_INIT to CPU.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SC_OEN_ST : SC Data Pin Output Enable Status (Read Only)
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SC_DATA_O : Output of SC Data Pin This bit is the pin status of SC data output but user can drive this pin to high or low by setting this bit. Note: When SC is at activation, warm re set or deactivation mode, this bit will be changed automatically. So don't fill this field when SC is in these modes.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CD_LEV : Card Detect Level\n\nNote: Software must select card detect level before Smart Card engine enable
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SC_DATA_I_ST : SC Data Input Pin Status (Read Only)\nThis bit is the pin status of SC_DATA_I
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CNT : Timer 0 Counter Value Register (ETU Base)\nThis field indicates the internal timer operation values.
bits : 0 - 23 (24 bit)
access : read-write

MODE : Timer 0 Operation Mode Selection
bits : 24 - 27 (4 bit)
access : read-write

CNT : Timer 1 Counter Value Register (ETU Base)\nThis field indicates the internal timer operation values.
bits : 0 - 7 (8 bit)
access : read-write

MODE : Timer 1 Operation Mode Selection
bits : 24 - 27 (4 bit)
access : read-write

CNT : Timer 2 Counter Value Register (ETU Base)\nThis field indicates the internal timer operation values.
bits : 0 - 7 (8 bit)
access : read-write

MODE : Timer 2 Operation Mode Selection
bits : 24 - 27 (4 bit)
access : read-write

UA_MODE_EN : UART Mode Enable Note1: When operating in UART mode, user must set SCx_CTL [CON_SEL] and SCx_CTL [AUTO_CON_EN] to 0 . Note2: When operating in smart card mode, user must set SCx_UACTL [7:0] register to 0 . Note3: When UART is enabled, hardware will generate a reset to reset internal buffer and internal state machine.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATA_LEN : Data Length
bits : 4 - 5 (2 bit)
access : read-write

PBDIS : Parity Bit Disable\nNote: In Smart Card mode, this field must be '0' (default setting is with parity bit)
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPE : Odd Parity Enable\nNote: This bit has effect only when PBDIS bit is '0'.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TDR0 : Timer0 Current Data Register (Read Only)\nThis field indicates the current count values of timer0.
bits : 0 - 23 (24 bit)
access : read-only

TDR1 : Timer1 Current Data Register (Read Only)\nThis field indicates the current count values of timer1.
bits : 0 - 7 (8 bit)
access : read-only

TDR2 : Timer2 Current Data Register (Read Only)\nThis field indicates the current count values of timer2.
bits : 8 - 15 (8 bit)
access : read-only

SC_CEN : SC Engine Enable Set this bit to 1 to enable SC operation. If this bit is cleared, SC will force all transition to IDLE state.
bits : 0 - 0 (1 bit)
access : read-write

DIS_RX : RX Transition Disable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIS_TX : TX Transition Disable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AUTO_CON_EN : Auto Convention Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CON_SEL : Convention Selection
bits : 4 - 5 (2 bit)
access : read-write

RX_FTRI_LEV : RX Buffer Trigger Level
bits : 6 - 7 (2 bit)
access : read-write

BGT : Block Guard Time (BGT)\nIn TX mode, hardware will auto hold off first character until BGT has elapsed regardless of the TX data.\n\nIn RX mode, software can enable SC_ALTCTL [RX_BGT_EN] to detect the first coming character timing. If the incoming data timing less than BGT, an interrupt will be generated.\n\nNote: The real block guard time is BGT + 1.
bits : 8 - 12 (5 bit)
access : read-write

TMR_SEL : Timer Selection
bits : 13 - 14 (2 bit)
access : read-write

SLEN : Stop Bit Length\nThis field indicates the length of stop bit.\nNote: The default stop bit length is 2.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RX_ERETRY : RX Error Retry Register\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred.\nNote1: The real maximum retry number is RX_ERETRY + 1, so 8 is the maximum retry number.\nNote2: This field can not be changed when RX_ERETRY_EN enabled. The change flow is to disable RX_ETRTRY_EN first and then fill new retry value.
bits : 16 - 18 (3 bit)
access : read-write

RX_ERETRY_EN : RX Error Retry Enable Register\nThis bit enables receiver retry function when parity error has occurred.\nNote: User must fill RX_ERETRY value before enabling this bit.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TX_ERETRY : TX Error Retry Register\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TX_ERETRY + 1, so 8 is the maximum retry number.\nNote2: This field can not be changed when TX_ERETRY_EN enabled. The change flow is to disable TX_ETRTRY_EN first and then fill new retry value.
bits : 20 - 22 (3 bit)
access : read-write

TX_ERETRY_EN : TX Error Retry Enable Register\nThis bit enables transmitter retry function when parity error has occurred.\nNote: User must fill TX_ERETRY value before enabling this bit.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CD_DEB_SEL : Card Detect De-Bounce Select Register
bits : 24 - 25 (2 bit)
access : read-write

TX_RST : TX Software Reset\nWhen TX_RST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared and needs at least 3 SC engine clock cycles.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RX_RST : RX Software Reset\nWhen RX_RST is set, all the bytes in the receiver buffer and RX internal state machine will be cleared.\nNote: This bit will be auto cleared and needs at least 3 SC engine clock cycles.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DACT_EN : Deactivation Sequence Generator Enable This bit enables SC controller to initiate the card by deactivation sequence Note1: When the deactivation sequence completed, this bit will be cleared automatically and the SC_ISR [INIT_IS] will be set to 1 . Note2: This field will be cleared by TX_RST and RX_RST. So don't fill this bit, TX_RST, and RX_RST at the same time. Note3: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACT_EN : Activation Sequence Generator Enable This bit enables SC controller to initiate the card by activation sequence Note1: When the activation sequence completed, this bit will be cleared automatically and the SC_IS [INIT_IS] will be set to 1 . Note2: This field will be cleared by TX_RST and RX_RST, so don't fill this bit, TX_RST, and RX_RST at the same time. Note3: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WARST_EN : Warm Reset Sequence Generator Enable This bit enables SC controller to initiate the card by warm reset sequence Note1: When the warm reset sequence completed, this bit will be cleared automatically and the SC_ISR [INIT_IS] will be set to 1 . Note2: This field will be cleared by TX_RST and RX_RST, so don't fill this bit, TX_RST, and RX_RST at the same time. Note3: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0_SEN : Internal Timer0 Start Enable This bit enables Timer0 to start counting. Software can fill 0 to stop it and set 1 to reload and count. Note3: This field will be cleared by TX_RST and RX_RST. So don't fill this bit, TX_RST and RX_RST at the same time. Note4: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1_SEN : Internal Timer1 Start Enable This bit enables Timer 1 to start counting. Software can fill 0 to stop it and set 1 to reload and count. Note3: This field will be cleared by TX_RST and RX_RST, so don't fill this bit, TX_RST, and RX_RST at the same time. Note4: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR2_SEN : Internal Timer2 Start Enable This bit enables Timer2 to start counting. Software can fill 0 to stop it and set 1 to reload and count. Note3: This field will be cleared by TX_RST and RX_RST. So don't fill this bit, TX_RST, and RX_RST at the same time. Note4: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INIT_SEL : Initial Timing Selection
bits : 8 - 9 (2 bit)
access : read-write

RX_BGT_EN : Receiver Block Guard Time Function Enable
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0_ATV : Internal Timer0 Active State (Read Only)\nThis bit indicates the timer counter status of timer0.
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TMR1_ATV : Internal Timer1 Active State (Read Only)\nThis bit indicates the timer counter status of timer1.
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TMR2_ATV : Internal Timer2 Active State (Read Only)\nThis bit indicates the timer counter status of timer2.
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

EGT : Extended Guard Time\nThis field indicates the extended guard timer value.\n\nNote: The counter is ETU based and the real extended guard time is EGT.
bits : 0 - 7 (8 bit)
access : read-write