SPI_CTL

SPI_RX0

SPI_RX1

SPI_TX0

SPI_TX1

SPI_VARCLK

SPI_DMA

SPI_FFCTL

SPI_STATUS

SPI_INTERNAL

SPI_CLKDIV

SPI_SSR

GO_BUSY : SPI Transfer Control Bit and Busy Status If the FIFO mode is disabled, during the data transfer, this bit keeps the value of '1'. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status. In FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In slave mode, this bit always returns 1 when software reads this register. In master mode, this bit reflects the busy or idle status of SPI. Note: When FIFO mode is disabled, all configurations should be set before writing 1 to the GO_BUSY bit in the SPI_CTL register. When FIFO bit is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA controller finishes the data transfer.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RX_NEG : Receive At Negative Edge
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TX_NEG : Transmit At Negative Edge
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TX_BIT_LEN : Transmit Bit Length
bits : 3 - 7 (5 bit)
access : read-write

LSB : Send LSB First
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKP : Clock Polarity
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SP_CYCLE : Suspend Interval (Master Only)\nIf the Variable Clock function is enabled, the minimum period of suspend interval (the transmit data in FIFO buffer is not empty) between the successive transaction is (6.5 + SP_CYCLE) * SPICLK clock cycle.
bits : 12 - 15 (4 bit)
access : read-write

INTEN : Interrupt Enable
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SLAVE : Slave Mode
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REORDER : Byte Reorder Function Enable
bits : 19 - 19 (1 bit)
access : read-write

FIFOM : FIFO Mode Enable Note: Before enabling FIFO mode, the other related settings should be set in advance. In Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set 1 automatically after the data was written into the 8-depth FIFO. The user can clear this FIFO bit after the transmit FIFO status is empty and the GO_BUSY back to 0.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TWOB : 2-bit Transfer Mode Active\nNote that when enabling TWOB, the serial transmitted 2-bits data are from SPI_TX1/0, and the received 2-bits data input are put into SPI_RX1/0.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VARCLK_EN : Variable Clock Enable\nNote: When this VARCLK_EN bit is set to 1, the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode).
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DUAL_IO_DIR : Dual IO Mode Direction
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DUAL_IO_EN : Dual IO Mode Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKEUP_EN : Wake-Up Enable\nWhen the system enters Power-down mode, the system can be wake-up from the SPI controller when this bit is enabled and if there is any toggle in the SPICLK port. After the system wake-up, this bit must be cleared by user to disable the wake-up requirement.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RDATA : Receive Data FIFO Register\nThe received data can be read on it. If the FIFO bit is set as 1, the user also checks the RX_EMPTY, SPI_STATUS[0], to check if there is any more received data or not. \nNote: These registers are read only.
bits : 0 - 31 (32 bit)
access : read-only

TDATA : Transmit Data FIFO Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bit SPI_TX[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: When the SPI controller is configured as a slave device and the FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the software must update the transmit data register before setting the GO_BUSY bit to 1.
bits : 0 - 31 (32 bit)
access : write-only

VARCLK : Variable Clock Pattern Flag\nThe value in this field is the frequency patterns of the SPICLK. If the bit pattern of VARCLK is '0', the output frequency of SPICLK is according the value of DIVIDER1. If the bit patterns of VARCLK are '1', the output frequency of SPICLK is according the value of DIVIDER2.
bits : 0 - 31 (32 bit)
access : read-write

TX_DMA_EN : Transmit PDMA Enable (PDMA Writes Data to SPI) Set this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. If using PDMA mode to transfer data, remember not to set GO_BUSY bit of SPI_CNTRL register. The DMA controller inside SPI controller will set it automatically whenever necessary. Note: 1. Two transaction need minimal 18 APB clock + 8 SPI serial clocks suspend interval in master mode for edge mode and 18 APB clock + 9.5 serial clocks for lev 2. If the 2-bit function is enabled, the requirement timing shall append 18 APB clock based on the above clock period. Hardware will clear this bit to 0 automatically after PDMA transfer done.
bits : 0 - 0 (1 bit)
access : read-write

RX_DMA_EN : Receiving PDMA Enable(PDMA Reads SPI Data to Memory) Set this bit to 1 will start the receive PDMA process. SPI controller will issue request to PDMA controller automatically when there is data written into the received buffer or the status of RX_EMPTY status is set to 0 in FIFO mode. If using the RX_PDMA mode to receive data but TX_DMA is disabled, the GO_BUSY bit shall be set by user. Hardware will clear this bit to 0 automatically after PDMA transfer done. In Slave mode and the FIFO bit is disabled, if the receive PDMA is enabled but the transmit PDMA is disabled, the minimal suspend interval between two successive transactions input is need to be larger than 9 SPI slave engine clock + 4 APB clock for edge mode and 9.5 SPI slave engine clock + 4 APB clock.
bits : 1 - 1 (1 bit)
access : read-write

PDMA_RST : PDMA Reset It is used to reset the SPI PDMA function into default state. Note: it is auto cleared to 0 after the reset function done.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RX_CLR : Receiving FIFO Counter Clear This bit is used to clear the receiver counter in FIFO Mode. This bit can be written 1 to clear the receiver counter and this bit will be cleared to 0 automatically after clearing receiving counter. After the clear operation, the flag of RX_EMPTY in SPI_STATUS[0] will be set to 1 .
bits : 0 - 0 (1 bit)
access : read-write

TX_CLR : Transmitting FIFO Counter Clear This bit is used to clear the transmit counter in FIFO Mode. This bit can be written 1 to clear the transmitting counter and this bit will be cleared to 0 automatically after clearing transmitting counter. After the clear operation, the flag of TX_EMPTY in SPI_STATUS[2] will be set to 1 .
bits : 1 - 1 (1 bit)
access : read-write

RXINT_EN : RX Threshold Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXINT_EN : TX Threshold Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXOVINT_EN : RX FIFO Over Run Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIMEOUT_EN : RX Read timeout function enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RX_THRESHOLD : Received FIFO Threshold 3-bits register, value from 0 ~7. If RX valid data counts large than RXTHRESHOLD, RXINT_STS will set to 1, else RXINT_STS will set to 0.
bits : 24 - 26 (3 bit)
access : read-write

TX_THRESHOLD : Transmit FIFO Threshold 3-bit register, value from 0 ~7. If TX valid data counts small or equal than TXTHRESHOLD, TXINT_STS will set to 1, else TXINT_STS will set to 0.
bits : 28 - 30 (3 bit)
access : read-write

RX_EMPTY : Received FIFO_EMPTY Status
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RX_FULL : Received FIFO_FULL Status
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TX_EMPTY : Transmitted FIFO_EMPTY Status
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TX_FULL : Transmitted FIFO_FULL Status
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LTRIG_FLAG : Level Trigger Accomplish Flag (INTERNAL ONLY)\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done.\nNote: This bit is READ only. As the software sets the GO_BUSY bit to 1, the LTRIG_FLAG will be cleared to 0 after 4 SPI engine clock periods plus 1 system clock period. In FIFO mode, this bit is unmeaning.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SLV_START_INTSTS : Slave Start Interrupt Status\nIt is used to dedicate that the transfer has started in Slave mode with no slave select.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSTS : Interrupt Status Note: This bit is read only, but can be cleared by writing 1 to this bit.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXINT_STS : RX FIFO Threshold Interrupt Status (Read Only)
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RX_OVER_RUN : RX FIFO Over Run Status\nIf SPI receives data when RX FIFO is full, this bit will set to 1, and the received data will dropped.\nNote: This bit will be cleared by writing 1 to itself.
bits : 9 - 9 (1 bit)
access : read-write

TXINT_STS : TX FIFO Threshold Interrupt Status (Read Only)
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TIME_OUT_STS : TIMEOUT Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RX_FIFO_CNT : Data counts in RX FIFO (Read Only)
bits : 16 - 19 (4 bit)
access : read-only

TX_FIFO_CNT : Data counts in TX FIFO (Read Only)
bits : 20 - 23 (4 bit)
access : read-only

DIVIDER1 : Clock Divider 1 Register \nThe value in this field is the 1th frequency divider of the PCLK to generate the serial clock of SPI_SCLK. The desired frequency is obtained according to the following equation: \nWhere\n is the SPI engine clock source. It is defined in the CLK_SEL1.
bits : 0 - 7 (8 bit)
access : read-write

DIVIDER2 : Clock Divider 2 Register \nThe value in this field is the 2nd frequency divider of the PCLK to generate the serial clock of SPI_SCLK. The desired frequency is obtained according to the following equation:
bits : 16 - 23 (8 bit)
access : read-write

SSR : Slave Select Active Register (Master Only) If AUTOSS bit is cleared, writing 1 to SSR[0] bit sets the SPISS[0] line to an active state and writing 0 sets the line back to inactive state.(the same as SSR[1] for SPISS[1]) If AUTOSS bit is set, writing 1 to any bit location of this field will select appropriate SPISS[1:0] line to be automatically driven to active state for the duration of the transaction, and will be driven to inactive state for the rest of the time. (The active level of SPISS[1:0] is specified in SS_LVL). Note: 1. This interface can only drive one device/slave at a given time. Therefore, the slaves select of the selected device must be set to its active level before starting any read or write transfer. 2. SPISS[0] is also defined as device/slave select input in Slave mode. And that the slave select input must be driven by edge active trigger which level depend on the SS_LVL setting, otherwise the SPI slave core will go into dead path until the edge active triggers again or reset the SPI core by software.
bits : 0 - 1 (2 bit)
access : read-write

SS_LVL : Slave Select Active Level\nIt defines the active level of device/slave select signal (SPISS[1:0]).
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AUTOSS : Automatic Slave Selection (Master Only)
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SS_LTRIG : Slave Select Level Trigger
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NOSLVSEL : No Slave Selected in Slave Mode This is used to ignore the slave select signal in Slave mode. The SPI controller can work on 3 wire interface including SPICLK, SPI_MISO, and SPI_MOSI when it is set as a slave device. Note: In no slave select signal mode, the SS_LTRIG, SPI_SSR[4], shall be set as 1 .
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SLV_ABORT : Abort in Slave Mode with No Slave Selected In normal operation, there is interrupt event when the received data meet the required bits which define in TX_BIT_LEN. If the received bits are less than the requirement and there is no more serial clock input over the time period which is defined by user in slave mode with no slave select, the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event. Note: It is auto cleared to 0 by hardware when the abort event is active.
bits : 8 - 8 (1 bit)
access : read-write

SSTA_INTEN : Slave Start Interrupt Enable\nIt is used to enable interrupt when the transfer has started in Slave mode with no slave select. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SS_INT_OPT : Slave Select Interrupt Option \nIt is used to enable the interrupt when the transfer has done in slave mode.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.