TMR_CTL

TMR_ISR

TMR_DR

TMR_TCAP

TMR_PRECNT

TMR_CMPR

TMR_IER

TMR_EN : Timer Counter Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

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SW_RST : Software Reset\nSet this bit will reset the timer counter, pre-scale counter and also force TMR_CTL [TMR_EN] to 0.\nNote: This bit will be auto cleared and takes at least 3 TMRx_CLK clock cycles.
bits : 1 - 1 (1 bit)
access : read-write

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WAKE_EN : Wake-up Enable\nWhen WAKE_EN is set and the TMR_IS or TCAP_IS is set, the timer controller will generate a wake-up trigger event to CPU.
bits : 2 - 2 (1 bit)
access : read-write

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DBGACK_EN : ICE Debug Mode Acknowledge Ineffective Enable
bits : 3 - 3 (1 bit)
access : read-write

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MODE_SEL : Timer Operating Mode Select
bits : 4 - 5 (2 bit)
access : read-write

TMR_ACT : Timer Active Status Bit (Read Only)\nThis bit indicates the timer counter status of timer.
bits : 7 - 7 (1 bit)
access : read-only

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ADC_TEEN : TMR_IS or TCAP_IS Trigger ADC Enable\nThis bit controls if TMR_IS or TCAP_IS could trigger ADC.\nWhen ADC_TEEN is set, TMR_IS is set and the CAP_TRG_EN is low, the timer controller will generate an internal trigger event to ADC controller.\nWhen ADC_TEEN is set, TCAP_IS is set and the CAP_TRG_EN is high, the timer controller will generate an internal trigger event to ADC controller.
bits : 8 - 8 (1 bit)
access : read-write

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DAC_TEEN : TMR_IS or TCAP_IS Trigger DAC Enable\nThis bit controls if TMR_IS or TCAP_IS could trigger DAC.\nWhen DAC_TEEN is set, TMR_IS is set and the CAP_TRG_EN is low, the timer controller will generate an internal trigger event to DAC controller.\nWhen DAC_TEEN is set, TCAP_IS is set and the CAP_TRG_EN is high, the timer controller will generate an internal trigger event to DAC controller.
bits : 9 - 9 (1 bit)
access : read-write

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PDMA_TEEN : TMR_IS or TCAP_IS Trigger PDMA Enable\nThis bit controls if TMR_IS or TCAP_IS could trigger PDMA.\nWhen PDMA_TEEN is set, TMR_IS is set and the CAP_TRG_EN is low, the timer controller will generate an internal trigger event to PDMA controller.\nWhen PDMA_TEEN is set, TCAP_IS is set and the CAP_TRG_EN is high, the timer controller will generate an internal trigger event to PDMA controller.
bits : 10 - 10 (1 bit)
access : read-write

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CAP_TRG_EN : TCAP_IS Trigger Mode Enable\nThis bit controls if the TMR_IS or TCAP_IS is used to trigger PDMA, DAC and ADC while TMR_IS or TCAP_IS is set.\nIf this bit is low and TMR_IS is set, timer will generate an internal trigger event to PDMA, DAC or ADC while related trigger enable bit (PDMA_TEEN, DAC_TEEN or ADC_TEEN) is also set.\nIf this bit is set high and TCAP_IS is set, timer will generate an internal trigger event to PDMA, DAC or ADC while related trigger enable bit (PDMA_TEEN, DAC_TEEN or ADC_TEEN) is also set.
bits : 11 - 11 (1 bit)
access : read-write

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EVENT_EN : Event Counting Mode Enable\nWhen EVENT_EN is set, the increase of 24-bit up-counting timer is controlled by external event pin.\nWhile the transition of external event pin matches the definition of EVENT_EDGE, the 24-bit up-counting timer increases by 1. Or, the 24-bit up-counting timer will keep its value unchanged.
bits : 12 - 12 (1 bit)
access : read-write

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EVENT_EDGE : Event Counting Mode Edge Selection\nThis bit indicates which edge of external event pin enabling the timer to increase 1.
bits : 13 - 13 (1 bit)
access : read-write

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EVNT_DEB_EN : External Event De-bounce Enable\nWhen EVNT_DEB_EN is set, the external event pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.\nIn de-bounce circuit the external event pin will be sampled 4 times by TMRx_CLK.\nNote: When EVENT_EN is enabled, enable this bit is recommended. And, while EVENT_EN is disabled, disable this bit is recommended to save power consumption.
bits : 14 - 14 (1 bit)
access : read-write

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TCAP_EN : Tcapture Pin Functional Enable\nThis bit controls if the transition on Tcapture pin could be used as timer counter reset function or timer capture function.\nNote: For TMRx_CTL, if INTR_TRG_EN is set, the TCAP_EN will be forced to low and the Tcapture pin transition is ignored.\nNote: For TMRx+1_CTL, if INTR_TRG_EN is set, the TCAP_EN will be forced to high.
bits : 16 - 16 (1 bit)
access : read-write

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TCAP_MODE : Tcapture Pin Function Mode Selection\nThis bit indicates if the transition on Tcapture pin is used as timer counter reset function or timer capture function.\nNote: For TMRx+1_CTL, if INTR_TRG_EN is set, the TCAP_MODE will be forced to low.
bits : 17 - 17 (1 bit)
access : read-write

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TCAP_EDGE : Tcapture Pin Edge Detect Selection
bits : 18 - 19 (2 bit)
access : read-write

CAP_CNT_MOD : Timer Capture Counting Mode Selection\nThis bit indicates the behavior of 24-bit up-counting timer while TCAP_EN is set to high.\nIf this bit is 0, the free-counting mode, the behavior of 24-bit up-counting timer is defined by MODE_SEL field. When TCAP_EN is set, TCAP_MODE is 0, and the transition of Tcapture pin matches the TCAP_EDGE setting, the value of 24-bit up-counting timer will be saved into register TMRx_TCAPn.\nIf this bit is 1, Trigger-counting mode, 24-bit up-counting timer will be not counting and keep its value at zero. When TCAP_EN is set, TCAP_MODE is 0, and once the transition of external pin matches the 1st transition of TCAP_EDGE setting, the 24-bit up-counting timer will start counting. And then if the transition of external pin matches the 2nd transition of TCAP_EDGE setting, the 24-bit up-counting timer will stop counting. And its value will be saved into register TMRx_TCAPn.\nNote: For TMRx+1_CTL, if INTR_TRG_EN is set, the CAP_CNT_MOD will be forced to high, the capture with Trigger-counting Timer mode.
bits : 20 - 20 (1 bit)
access : read-write

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CAP_DEB_EN : Tcapture Pin De-bounce Enable\nWhen CAP_DEB_EN is set, the Tcapture pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.\nIn de-bounce circuit the Tcapture pin signal will be sampled 4 times by TMRx_CLK.\nNote: When TCAP_EN is enabled, enable this bit is recommended. And, while TCAP_EN is disabled, disable this bit is recommended to save power consumption.
bits : 22 - 22 (1 bit)
access : read-write

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INTR_TRG_EN : Inter-Timer Trigger Mode Enable\nThis bit controls if Inter-timer Trigger mode is enabled.\nIf Inter-timer Trigger mode is enabled, the TMRx will be in counter mode and counting with external Clock Source or event. And, TMRx+1 will be in trigger-counting mode of capture function.\nNote: For TMRx+1_CTL, this bit is ignored and the read back value is always 1'b0.
bits : 24 - 24 (1 bit)
access : read-write

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TMR_IS : Timer Interrupt Status\nThis bit indicates the interrupt status of Timer.\nThis bit is set by hardware when the up counting value of internal 24-bit counter matches the timer compared value (TMR_CMPR). Write 1 to clear this bit to 0.\nIf this bit is active and TMR_IE is enabled, Timer will trigger an interrupt to CPU.
bits : 0 - 0 (1 bit)
access : read-write

TCAP_IS : Timer Capture Function Interrupt Status\nThis bit indicates the external pin function interrupt status of Timer.\nThis bit is set by hardware when TCAP_EN is set high, and the transition of external pin matches the TCAP_EDGE setting. Write 1 to clear this bit to zero.\nIf this bit is active and TCAP_IE is enabled, Timer will trigger an interrupt to CPU.
bits : 1 - 1 (1 bit)
access : read-write

TMR_Wake_STS : Timer Wake-up Status\nIf timer causes CPU wakes up from power-down mode, this bit will be set to high. It must be cleared by software with a write 1 to this bit.
bits : 4 - 4 (1 bit)
access : read-write

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NCAP_DET_STS : New Capture Detected Status\nThis status is to indicate there is a new incoming capture event detected before CPU clearing the TCAP_IS status.\nIf the above condition occurred, the Timer will keep register TMRx_CAP unchanged and drop the new capture value.\nThis bit is also cleared to 0 while TCAP_IS is cleared.
bits : 5 - 5 (1 bit)
access : read-write

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TDR : Timer Data Register\nUser can read this register for internal 24-bit timer up-counter value.
bits : 0 - 23 (24 bit)
access : read-only

CAP : Timer Capture Data Register\nWhen TCAP_EN is set, TCAP_MODE is 0, and the transition of external pin matches the TCAP_EDGE setting, the value of 24-bit up-counting timer will be saved into register TMRx_TCAP. User can read this register for the counter value.
bits : 0 - 23 (24 bit)
access : read-only

PRESCALE_CNT : Pre-scale Counter
bits : 0 - 7 (8 bit)
access : read-write

TMR_CMP : Timer Compared Value\nTMR_CMP is a 24-bit compared register. When the internal 24-bit up-counter counts and its value is equal to TMR_CMP value, a Timer Interrupt is requested if the timer interrupt is enabled with TMR_IER [TMR_IE] is enabled. The TMR_CMP value defines the timer counting cycle time.\nNote1: Never write 0x0 or 0x1 in TMR_CMP, or the core will run into unknown state.\nNote2: No matter TMR_CTL [TMR_EN] is 0 or 1, whenever software write a new value into this register, TIMER will restart counting using this new value and abort previous count.
bits : 0 - 23 (24 bit)
access : read-write

TMR_IE : Timer Interrupt Enable\nNote: If timer interrupt is enabled, the timer asserts its interrupt signal when the associated counter is equal to TMR_CMPR.
bits : 0 - 0 (1 bit)
access : read-write

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TCAP_IE : Timer Capture Function Interrupt Enable\nNote: If timer external pin function interrupt is enabled, the timer asserts its interrupt signal when the TCAP_EN is set and the transition of external pin matches the TCAP_EDGE setting
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.