UART_RBR

UART_THR

UART_ISR

UART_TRSR

UART_FSR

UART_MCSR

UART_TMCTL

UART_BAUD

UART_IRCR

UART_ALT_CSR

UART_FUN_SEL

UART_CTL

UART_TLCTL

UART_IER

RBR : Receive Buffer Register\nBy reading this register, the UART will return an 8-bit data received from RX pin (LSB first).
bits : 0 - 7 (8 bit)
access : read-only

THR : Transmit Holding Register\nBy writing to this register, the UART will send out an 8-bit data through the TX pin (LSB first).
bits : 0 - 7 (8 bit)
access : write-only

RDA_IS : Receive Data Available Interrupt Flag (Read Only).\nWhen the number of bytes in the RX-FIFO equals the RFITL then the RDA_IF will be set. If IER [RDA_IEN] is set then the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX-FIFO drops below the threshold level (RFITL).
bits : 0 - 0 (1 bit)
access : read-only

THRE_IS : Transmit Holding Register Empty Interrupt Flag (Read Only). \nThis bit is set when the last data of TX-FIFO is transferred to Transmitter Shift Register. If IER [THRE_IEN] is set that the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX-FIFO not empty).
bits : 1 - 1 (1 bit)
access : read-only

RLS_IS : Receive Line Interrupt Status Flag (Read Only).\nThis bit is set when the RX received data has parity error (UART_FSR [PE_F]), framing error (UART_FSR [FE_F]), break error (UART_FSR [BI_F]) or RS-485 detect address byte (UART_TRSR [RS-485_ADDET_F]).If IER [RLS_IEN] is set then the RLS interrupt will be generated.\nNote1: This bit is read only, but can be cleared by it by writing "1" to UART_FSR [BI_F], UART_FSR [FE_F], UART_FSR [PE_F] or UART_TRSR [RS-485_ADDET_F].\nNote2: This bit is cleared when both the BI_F, FE_F, PE_F and RS-485_ADDET_F are cleared.
bits : 2 - 2 (1 bit)
access : read-only

MODEM_IS : MODEM Interrupt Status Flag (Read Only) \nNote: This bit is read only, but can be cleared by it by writing "1" to UART_MCSR [DCT_F].
bits : 3 - 3 (1 bit)
access : read-only

RTO_IS : RX Time-Out Interrupt Status Flag (Read Only)\nThis bit is set when the RX-FIFO is not empty and no activities occur in the RX-FIFO and the time-out counter equal to TOIC. If IER [Tout_IEN] is set then the tout interrupt will be generated. \nNote: This bit is read only and user can read UART_RBR (RX is in active) to clear it.
bits : 4 - 4 (1 bit)
access : read-only

BUF_ERR_IS : Buffer Error Interrupt Status Flag (Read Only)\nThis bit is set when the TX or RX-FIFO overflowed. When BUF_ERR_IS is set, the transfer maybe not correct. If IER [BUF_ER_IEN] is set then the buffer error interrupt will be generated.\nNote1: This bit is read only, but can be cleared by it by writing "1" to UART_FSR [TX_OVER_F] or UART_FSR [RX_OVER_F].\nNote2: This bit is cleared when both the TX_OVER_F and RX_OVER_F are cleared.
bits : 5 - 5 (1 bit)
access : read-only

WAKE_IS : Wake-Up Interrupt Status Flag (Read Only)\nThis bit is set in Power-down mode, the receiver received data or CTSn signal. If IER [WAKE_IE] is set then the wake-up interrupt will be generated.\nNote: This bit is read only, but can be cleared by it by writing "1" to it.
bits : 6 - 6 (1 bit)
access : read-only

ABAUD_IS : Auto-Baud Rate Interrupt Status Flag (Read Only)\nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if IER [ABAUD_IE] is set then the auto-baud rate interrupt will be generated.\nNote1: This bit is read only, but can be cleared by it by writing "1" to UART_TRSR [ABAUD_TOUT_F] or UART_TRSR [ABAUD_F].\nNote2: This bit is cleared when both the ABAUD_TOUT_F and ABAUD_F are cleared.
bits : 7 - 7 (1 bit)
access : read-only

LIN_IS : LIN Interrupt Status Flag (Read Only)\nThis bit is set when the LIN TX header transmitted, RX header received or the SIN does not equal SOUT and if IER [LIN_IE] is set then the LIN interrupt will be generated. \nNote1: This bit is read only, but can be cleared by it by writing "1" to UART_TRSR [BIT_ERR_F], UART_TRSR [BIT_TX_F] or UART_TRSR [LIN_RX_F].\nNote2: This bit is cleared when both the BIT_ERR_F, BIT_TX_F and LIN_RX_F are cleared.
bits : 8 - 8 (1 bit)
access : read-only

RS_485_ADDET_F : RS-485 Address Byte Detection Status Flag (Read Only)\nNote1: This field is used for RS-485 mode.\nNote2: This bit is read only, but can be cleared by writing "1" to it.
bits : 0 - 0 (1 bit)
access : read-only

ABAUD_F : Auto-Baud Rate Interrupt (Read Only)\nThis bit is set to logic "1" when auto-baud rate detect function finished.\nNote: This bit is read only, but can be cleared by writing "1" to it.
bits : 1 - 1 (1 bit)
access : read-only

ABAUD_TOUT_F : Auto-Baud Rate Time-Out Interrupt (Read Only)\nThis bit is set to logic "1" in Auto-baud Rate Detect mode and the baud rate counter is overflow.\nNote: This bit is read only, but can be cleared by writing "1" to it.
bits : 2 - 2 (1 bit)
access : read-only

LIN_TX_F : LIN TX Interrupt Flag (Read Only)\nThis bit is set to logic "1" when LIN transmitted header field. The header may be "break field" or "break field + sync field" or "break field + sync field + PID field", it can be choose by setting UART_ALT_CTL[LIN_HEAD_SEL] register.\nNote: This bit is read only, but can be cleared by writing "1" to it.
bits : 3 - 3 (1 bit)
access : read-only

LIN_RX_F : LIN RX Interrupt Flag (Read Only)\nThis bit is set to logic "1" when received LIN header field. The header may be "break field" or "break field + sync field" or "break field + sync field + PID field", and it can be choose by setting UART_ALT_CTL [LIN_HEAD_SEL] register.\nIf the field includes "break field", when the receiver received break field then the LIN_RX_F will be set. The controller will receive next data and put it in FIFO.\nIf the field includes "break field + sync field", hardware will wait for the flag LIN_RX_F in UART_TRSR to check RX received break field and sync field. If the break and sync field is received, hardware will set UART_TRSR [LIN_RX_F] flag, and if the break is received but the sync field does not equal 0x55, then hardware will set UART_TRSR [LIN_RX_F] and UART_TRSR [LIN_RX_SYNC_ERR_F] flag. The break and sync data (equals 0x55 or not) will not be stored in FIFO.\nIf the field includes "break field + sync field + PID field", In this operation mode, hardware will control data automatically. Hardware will ignore any data until received break + sync (0x55) + PID value match the UART_ALT_CTL [ADDR_MATCH] value (break + sync + PID will not be stored in FIFO). When received break + sync (0x55) + PID value match the UART_ALT_CTL [ADDR_MATCH] value, hardware will set UART_TRSR [LIN_RX_F] and the following all data will be accepted and stored in the RX-FIFO until detect next break field. If the receiver received break + wrong sync (not equal 0x55) + PID value, hardware will set UART_TRSR [LIN_RX_F] and UART_TRSR [LIN_RX_SYNC_ERR_F] flag and the receiver will be disabled. If the receiver received break + sync (0x55) + wrong PID value, hardware will set UART_TRSR [LIN_RX_F] flag and the receiver will be disabled. \nNote: This bit is read only, but can be cleared by writing "1" to it.
bits : 4 - 4 (1 bit)
access : read-only

BIT_ERR_F : Bit Error Detect Status Flag (Read Only)\nAt TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state is not equal to the output pin (SOUT) state, BIT_ERR_F will be set.\nWhen occur bit error, hardware will generate an interrupt to CPU (INT_LIN).\nNote1: This bit is read only, but it can be cleared by writing "1" to it.
bits : 5 - 5 (1 bit)
access : read-only

LIN_RX_SYNC_ERR_F : LIN RX SYNC Error Flag (Read Only)\nThis bit is set to logic "1" when LIN received incorrect SYNC field. \nUser can choose the header by setting UART_ALT_CTL [LIN_HEAD_SEL] register.\nIf the field includes "break field + sync field" and if the sync data does not equal 0x55, the LIN_RX_F and LIN_RX_SYNC_ERR_F will be set and the wrong sync data will be ignored. The controller will receive next data and put it in FIFO. \nIf the field includes "break field + sync field + PID field" and if the sync data does not equal 0x55, the LIN_RX_F and LIN_RX_SYNC_ERR_F will be set and the wrong sync data will be ignored. The controller will receive next data and put it in FIFO. \nNote: This bit is read only, but can be cleared by writing "1" to LIN_RX_F.
bits : 8 - 8 (1 bit)
access : read-only

RX_OVER_F : RX Overflow Error Status Flag (Read Only) \nThis bit is set when RX-FIFO overflow.\nIf the number of bytes of received data is greater than RX-FIFO (UART_RBR) size, 16 bytes of UART0/UART1, this bit will be set.\nNote: This bit is read only, but it can be cleared by writing "1" to it.
bits : 0 - 0 (1 bit)
access : read-only

RX_EMPTY_F : Receiver FIFO Empty (Read Only)\nThis bit initiate RX-FIFO empty or not.\nWhen the last byte of RX-FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
bits : 1 - 1 (1 bit)
access : read-only

RX_FULL_F : Receiver FIFO Full (Read Only)\nThis bit initiates RX-FIFO full or not.\nThis bit is set when RX_POINTER_F is equal to 16, otherwise is cleared by hardware.
bits : 2 - 2 (1 bit)
access : read-only

PE_F : Parity Error State Status Flag (Read Only)\nThis bit is set to logic "1" whenever the received character does not have a valid "parity bit", and it is reset whenever the CPU writes "1" to this bit.\nNote: This bit is read only, but it can be cleared by writing "1" to it.
bits : 4 - 4 (1 bit)
access : read-only

FE_F : Framing Error Status Flag (Read Only)\nThis bit is set to logic "1" whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic "0"), and it is reset whenever the CPU writes "1" to this bit.\nNote: This bit is read only, but it can be cleared by writing "1" to it.
bits : 5 - 5 (1 bit)
access : read-only

BI_F : Break Status Flag (Read Only)\nThis bit is set to a logic "1" whenever the received data input(RX) is held in the "spacing state" (logic "0") for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and it is reset whenever the CPU writes "1" to this bit.\nNote: This bit is read only, but it can be cleared by writing "1" to it.
bits : 6 - 6 (1 bit)
access : read-only

TX_OVER_F : TX Overflow Error Interrupt Status Flag (Read Only)\nIf TX-FIFO (UART_THR) is full, an additional write to UART_THR will cause this bit to logic "1". \nNote: This bit is read only, but it can be cleared by writing "1" to it.
bits : 8 - 8 (1 bit)
access : read-only

TX_EMPTY_F : Transmitter FIFO Empty (Read Only)\nThis bit indicates TX-FIFO empty or not.\nWhen the last byte of TX-FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX-FIFO not empty).
bits : 9 - 9 (1 bit)
access : read-only

TX_FULL_F : Transmitter FIFO Full (Read Only)\nThis bit indicates TX-FIFO full or not.\nThis bit is set when TX_POINTER_F is equal to 16, otherwise is cleared by hardware.
bits : 10 - 10 (1 bit)
access : read-only

TE_F : Transmitter Empty Status Flag (Read Only)\nBit is set by hardware when TX is inactive. (TX shift register does not have data)\nBit is cleared automatically when TX-FIFO is transfer data to TX shift register or TX is empty but the transfer does not finish.
bits : 11 - 11 (1 bit)
access : read-only

RX_POINTER_F : RX-FIFO Pointer (Read Only)\nThis field indicates the RX-FIFO Buffer Pointer. When UART receives one byte from external device, RX_POINTER_F increases one. When one byte of RX-FIFO is read by CPU, RX_POINTER_F decreases one.
bits : 16 - 20 (5 bit)
access : read-only

TX_POINTER_F : TX-FIFO Pointer (Read Only)\nThis field indicates the TX-FIFO Buffer Pointer. When CPU writes one byte data into UART_THR, TX_POINTER_F increases one. When one byte of TX-FIFO is transferred to Transmitter Shift Register, TX_POINTER_F decreases one.
bits : 24 - 28 (5 bit)
access : read-only

LEV_RTS : RTSn Trigger Level
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTS_ST : RTSn Pin State (Read Only)\nThis bit is the pin status of RTSn.
bits : 1 - 1 (1 bit)
access : read-only

LEV_CTS : CTSn Trigger Level
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CTS_ST : CTSn Pin Status (Read Only)\nThis bit is the pin status of CTSn.
bits : 17 - 17 (1 bit)
access : read-only

DCT_F : Detect CTSn State Change Status Flag (Read Only)\nThis bit is set whenever CTSn input has change state, and it will generate Modem interrupt to CPU when UART_IER [Modem_IEN].\nNote: This bit is read only, but it can be cleared by writing "1" to it.
bits : 18 - 18 (1 bit)
access : read-only

TOIC : Time-Out Comparator\nNote1: Fill all "0" to this field indicates to disable this function.\nNote2: The real time-out value is TOIC + 1.\nNote3: The counting clock is baud rate clock.
bits : 0 - 8 (9 bit)
access : read-write

DLY : TX Delay Time Value\nThis field is use to program the transfer delay time between the last stop bit leaving the TX-FIFO and the de-assertion of by setting UART_TOR [DLY] register.\n\n\nNote1: Fill all "0" to this field indicates to disable this function.\nNote2: The real delay value is DLY.\nNote3: The counting clock is baud rate clock.
bits : 16 - 23 (8 bit)
access : read-write

BRD : Baud Rate Divider
bits : 0 - 15 (16 bit)
access : read-write

DIV_16_EN : Divider 16 Enable\nNote: In IrDA mode, this bit must disable.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TX_SELECT : TX_SELECT\nNote: In IrDA mode, the UART_BAUD [DIV_16_EN) register must be set (the baud equation must be Clock / 16 * (BRD)
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INV_TX : INV_TX
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INV_RX : INV_RX
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIN_TX_BCNT : LIN TX Break Field Count Register\nThe field contains 3-bit LIN TX break field count.\nNote: The break field length is LIN_TX_BCNT + 8.
bits : 0 - 2 (3 bit)
access : read-write

LIN_HEAD_SEL : LIN Header Selection\n
bits : 4 - 5 (2 bit)
access : read-write

LIN_RX_EN : LIN RX Enable\nWhen LIN RX mode enabled and received a break field or sync field or PID field (Select by LIN_Header_SEL), the controller will generator a interrupt to CPU (INT_LIN)
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIN_TX_EN : LIN TX Header Trigger Enable\nNote1: When TX header field (break field or break and sync field or break, sync and PID field) transfer operation finished, this bit will be cleared automatically and generate a interrupt to CPU (INT_LIN).\nNote2: If user wants to receive transmit data, it recommended to enable LIN_RX_EN bit.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

Bit_ERR_EN : Bit Error Detect Enable\nNote: In LIN function mode, when bit error occurs, hardware will generate an interrupt to CPU (INT_LIN).
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS_485_NMM : RS-485 Normal Multi-Drop Operation Mode (RS-485 NMM Mode)\nNote: It can't be active in RS-485_AAD Operation mode.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS_485_AAD : RS-485 Auto Address Detection Operation Mode (RS-485 AAD Mode)\nNote: It can't be active in RS-485_NMM Operation mode.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS_485_AUD : RS-485 Auto Direction Mode (RS-485 AUD Mode)\nNote: It can be active in RS-485_AAD or RS-485_NMM operation mode.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS_485_ADD_EN : RS-485 Address Detection Enable\nNote: This field is used for RS-485 any operation mode.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADDR_PID_MATCH : Address / PID Match Value Register\nThis field contains the RS-485 address match values in RS-485 Function mode.\nThis field contains the LIN protected identifier field n LIN Function mode, software fills ID0~ID5 (ADDR_PID_MATCH [5:0]), hardware will calculate P0 and P1.\n\nNote: This field is used for RS-485 auto address detection mode or used for LIN protected identifier field (PID).
bits : 24 - 31 (8 bit)
access : read-write

FUN_SEL : Function Select Enable
bits : 0 - 1 (2 bit)
access : read-write

RX_RST : RX Software Reset\nWhen RX_RST is set, all the bytes in the receiving FIFO and RX internal state machine are cleared.\nNote: This bit will be auto cleared and take at least 3 UART engine clock cycles.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TX_RST : TX Software Reset\nWhen TX_RST is set, all the bytes in the transmitting FIFO and TX internal state machine are cleared.\nNote: This bit will be auto cleared and take at least 3 UART engine clock cycles.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RX_DIS : Receiver Disable Register.\nThe receiver is disabled or not (set "1" to disable receiver)\nNote1: When used for RS-485 NMM mode, user can set this bit to receive data before detecting address byte.\nNote2: In RS-485 AAD mode and LIN "break + sync +PID" header mode, hardware will control data automatically, so don't fill any value to this bit.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TX_DIS : Transfer Disable Register.\nThe receiver is disabled or not (set "1" to disable receiver)
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AUTO_RTS_EN : RTSn Auto-Flow Control Enable \nNote: When RTSn auto-flow is enabled, if the number of bytes in the RX-FIFO equals the UART_FCR [RTS_Tri_Lev], the UART will reassert RTSn signal.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AUTO_CTS_EN : CTSn Auto-Flow Control Enable \nNote: When CTSn auto-flow is enabled, the UART will send data to external device when CTSn input assert (UART will not send data to device until CTSn is asserted).
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMA_RX_EN : RX DMA Enable \nThis bit can enable or disable RX PDMA service.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMA_TX_EN : TX DMA Enable \nThis bit can enable or disable TX PDMA service.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WAKE_CTS_EN : CTSn Wake-Up Function Enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WAKE_DATA_EN : Incoming Data Wake-up Function Enable \nNote: Hardware will clear this bit when the incoming data wake-up operation finishes and "system clock" work stable.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABAUD_EN : Auto-Baud Rate Detect Enable\nNote: When the auto-baud rate detect operation finishes, hardware will clear this bit and the associated interrupt (INT_ABAUD) will be generated (If UART_IER [ABAUD_IE] be enabled).
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATA_LEN : Data Length
bits : 0 - 1 (2 bit)
access : read-write

NSB : Number of STOP Bit Length
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PBE : Parity Bit Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EPE : Even Parity Enable\nNote: This bit has effect only when PBE bit (parity bit enable) is set.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPE : Stick Parity Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BCB : Break Control Bit \nWhen this bit is set to logic "1", the serial data output (TX) is forced to the Spacing State (logic "0"). This bit acts only on TX pin and has no effect on the transmitter logic.
bits : 6 - 6 (1 bit)
access : read-write

RFITL : RX-FIFO Interrupt (INT_RDA) Trigger Level
bits : 8 - 9 (2 bit)
access : read-write

RTS_TRI_LEV : RTSn Trigger Level (For Auto-flow Control Use)
bits : 12 - 13 (2 bit)
access : read-write

RDA_IE : Receive Data Available Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

THRE_IE : Transmit Holding Register Empty Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RLS_IE : Receive Line Status Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODEM_IE : Modem Status Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTO_IE : RX Time-Out Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUF_ERR_IE : Buffer Error Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WAKE_IE : Wake-Up Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABAUD_IE : Auto-Baud Rate Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIN_IE : LIN Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.