\n
address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
Window Watchdog Timer Reload Counter Register
address_offset : 0x0 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WWDTRLD : Window Watchdog Timer Reload Counter Register\nWriting 0x00005AA5 to this register will reload the Window Watchdog Timer counter value to 0x3F. \nNote: SW only can write WWDTRLD when WWDT counter value between 0 and WINCMP. If SW writes WWDTRLD when WWDT counter value larger than WINCMP, WWDT will generate RESET signal.
bits : 0 - 31 (32 bit)
access : write-only
Window Watchdog Timer Counter Value Register
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WWDTVAL : WWDT Counter Value\nThis register reflects the counter value of window watchdog. This register is read only
bits : 0 - 5 (6 bit)
access : read-only
Window Watchdog Timer Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WWDTEN : Window Watchdog Enable\nSet this bit to enable Window Watchdog timer.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Window Watchdog timer function Disabled
#1 : 1
Window Watchdog timer function Enabled
End of enumeration elements list.
PERIODSEL : WWDT Pre-scale Period Select\nThese three bits select the pre-scale for the WWDT counter period.\nPlease refer to Table 5 17
bits : 8 - 11 (4 bit)
access : read-write
WINCMP : WWDT Window Compare Register\nSet this register to adjust the valid reload window. \nNote: SW only can write WWDTRLD when WWDT counter value between 0 and WINCMP. If SW writes WWDTRLD when WWDT counter value larger than WWCMP, WWDT will generate RESET signal.
bits : 16 - 21 (6 bit)
access : read-write
DBGEN : WWDT Debug Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
WWDT stopped count if system is in Debug mode
#1 : 1
WWDT still counted even system is in Debug mode
End of enumeration elements list.
Window Watchdog Timer Interrupt Enable Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WWDTIE : WWDT Interrupt Enable\nSetting this bit will enable the Watchdog timer interrupt function.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Watchdog timer interrupt function Disabled
#1 : 1
Watchdog timer interrupt function Enabled
End of enumeration elements list.
Window Watchdog Timer Status Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WWDTIF : WWDT Compare Match Interrupt Flag\nWhen WWCMP match the WWDT counter, then this bit is set to 1. This bit will be cleared by software write 1 to this bit.
bits : 0 - 0 (1 bit)
access : read-write
WWDTRF : WWDT Reset Flag\nWhen WWDT counter down count to 0 or write WWDTRLD during WWDT counter larger than WINCMP, chip will be reset and this bit is set to 1. Software can write 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write
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