SYS_PDID (PDID)

SYS_REGLCTL (REGLCTL)

SYS_RPDBCLK (RPDBCLK)

SYS_TEMPCTL (TEMPCTL)

SYS_RCCFCTL (RCCFCTL)

SYS_GPA_MFPL (GPA_MFPL)

SYS_GPA_MFPH (GPA_MFPH)

SYS_GPB_MFPL (GPB_MFPL)

SYS_GPB_MFPH (GPB_MFPH)

SYS_RSTSTS (RSTSTS)

SYS_GPC_MFPL (GPC_MFPL)

SYS_GPC_MFPH (GPC_MFPH)

SYS_GPD_MFPL (GPD_MFPL)

SYS_GPD_MFPH (GPD_MFPH)

SYS_GPE_MFPL (GPE_MFPL)

SYS_GPF_MFPL (GPF_MFPL)

SYS_PORCTL (PORCTL)

SYS_BODCTL (BODCTL)

SYS_BODSTS (BODSTS)

SYS_IVREFCTL (IVREFCTL)

SYS_LDOCTL (LDOCTL)

SYS_BATDCTL (BATDCTL)

SYS_WKSTS (WKSTS)

SYS_IPRST1 (IPRST1)

SYS_RC0TCTL (RC0TCTL)

SYS_RC0TIEN (RC0TIEN)

SYS_RC0TISTS (RC0TISTS)

SYS_RC1TCTL (RC1TCTL)

SYS_RC1TIEN (RC1TIEN)

SYS_RC1TISTS (RC1TISTS)

SYS_MRCTCTL (MRCTCTL)

SYS_MRCTIEN (MRCTIEN)

SYS_MRCTISTS (MRCTISTS)

SYS_IPRST2 (IPRST2)

PDID : Part Device Identification Number (Read Only)\nThis register reflects device part number code. Software can read this register to identify which device is used.
bits : 0 - 31 (32 bit)
access : read-only

REGLCTL : Register Lock Control Code (Write Only) Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 59h , 16h , 88h to this field. After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. Register Lock Control Disable Index (Read Only)
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTPDBCLK : Reset Pin Debounce Clock Selection Bit\nBefore swtch clock, both clock sources must be enabled.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VTEMPEN : Temperature Sensor Enable Bit\nThis bit is used to enable/disable temperature sensor function.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HIRC0FEN : HIRC0 Clock Filter Enable Bit\nThis bit is used to enable/disable HIRC0clock filter function.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HIRC1FEN : HIRC1 Clock Filter Enable Bit\nThis bit is used to enable/disable HIRC1clock filter function.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MRCFEN : MRC Clock Filter Enable Bit\nThis bit is used to enable/disable MRC clock filter function.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA0MFP : PA.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA1MFP : PA.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA2MFP : PA.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA3MFP : PA.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA4MFP : PA.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA5MFP : PA.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA6MFP : PA.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA8MFP : PA.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA9MFP : PA.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA10MFP : PA.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA11MFP : PA.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA12MFP : PA.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA13MFP : PA.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA14MFP : PA.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA15MFP : PA.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB0MFP : PB.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB1MFP : PB.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB2MFP : PB.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB3MFP : PB.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB4MFP : PB.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB5MFP : PB.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB6MFP : PB.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB7MFP : PB.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB8MFP : PB.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB9MFP : PB.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB10MFP : PB.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB11MFP : PB.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB13MFP : PB.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB14MFP : PB.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB15MFP : PB.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PORF : POR Reset Flag The POR reset flag is set by the Reset Signal from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PINRF : NRESET Pin Reset Flag The nRESET pin reset flag is set by the Reset Signal from the nRESET Pin to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDTRF : WDT Reset Flag The WDT reset flag is set by the Reset Signal from the Watchdog Timer to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVRF : LVR Reset Flag The LVR reset flag is set by the Reset Signal from the Low-VoltageReset controller to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODRF : BOD Reset Flag The BOD reset flag is set by the Reset Signal from the Brown-Out Detector to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYSRF : System Reset Flag The system reset flag is set by the Reset Signal from the Cortex-M0 Core to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPURF : CPU Reset Flag\nThe CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M0 Core and Flash Memory Controller (FMC).\nNote: Write 1 to clear this bit to 0.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LOCKRF : Lockup Reset Flag
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PC0MFP : PC.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PC1MFP : PC.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PC2MFP : PC.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PC3MFP : PC.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PC6MFP : PC.6 Pin Fuction Selection
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PC7MFP : PC.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PC8MFP : PC.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PC9MFP : PC.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PC10MFP : PC.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PC11MFP : PC.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PC14MFP : PC.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PC15MFP : PC.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PD6MFP : PD.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PD7MFP : PD.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PD14MFP : PD.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PD15MFP : PD.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PE5MFP : PE.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PF0MFP : PF.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PF1MFP : PF.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PF2MFP : PF.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PF3MFP : PF.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PF6MFP : PF.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PF7MFP : PF.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POROFF : Power-on Reset Enable Bit (Write Protect)\nWhen powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.\nThe POR function will be active again when this field is set to another value or chip is reset by other reset source, including:\nnRESET, Watchdog, BOD reset, ICE reset command and the software-chip reset function.\nNote:This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 15 (16 bit)
access : read-write

BODEN : Brown-out Detector Enable Bit (Write Protect)\nThe default value is set by flash controller user configuration register CBODEN (CONFIG0 []).This Brown-out Detecto only valid in Normal Mode.\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: LIRC must be enabled before enable BOD.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODIE : BOD Interrupt Enable Control(Write Protect)\nNote1: While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high.\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODREN : Brown-out Reset Enable Bit (Write Protect)\nThe default value is set by flash controller user configuration register CBOV(CONFIG0[]) bit.\nNote1: While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high).\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODIF : Brown-out DetectorInterrupt Flag\nNote: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODOUT : Brown-out DetectorOutuput Status\nIt means the detected voltage is lower than BODVL setting. If the BODEN is 0, BOD function disabled , this bit always responds 0.\nNote: This bit is ready-only.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVREN : Low Voltage Reset Enable Bit (Write Protect)\nThe LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.\nNote1: After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default).\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote3: LIRC must be enabled before enable LVR.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LPBODEN : Low Power Brown-out Detector Enable Bit (Write Protect)\nLow Power Brown-out Dector only valid in Power-down mode.\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: LIRC must be enabled before enable BOD.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LPBODVL : Low Power Brown-out Detector Threshold Voltage Selection(Write Protect)\nLow Power Brown-out Dector only valid in Power-down mode.\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LPBODIE : Low Power BOD Interrupt Enable Control(Write Protect)\nLow Power Brown-out Dector only valid in Power-down mode.\nNote1: While the LPBOD function is enabled (LPBODEN high) and LPBOD interrupt function is enabled (LPBODIEhigh), LPBOD will assert an interrupt if BODOUT is high. Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LPBODREN : Low Power Brown-out Reset Enable Bit (Write Protect)\nLow Power Brown-out Dector only valid in Power-down mode.\nNote1: While the Low power Brown-out Detector function is enabled (LPBODEN high) and LPBOD reset function is enabled (LPBODREN high), LPBOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high).\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODVL : Brown-out Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by flash controller user configuration register CBOV (CONFIG0[]).\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 12 - 15 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LPBOD20TRIM : Low Power BOD 2.0 TRIM Value(Write Protect) This value is used to control BOD20 detect voltage level in power-down mode, nominal 2.0 V. Higher trim value, higher detection voltage. Note: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 16 - 19 (4 bit)
access : read-write

LPBOD25TRIM : Low Power BOD 2.5 TRIM Value(Write Protect) This value is used to control LPBOD25 detect voltage level in power-down mode, nominal 2.5 V. Higher trim value, higher detection voltage. Note: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 20 - 23 (4 bit)
access : read-write

BODDGSEL : Brown-out Detector Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVRDGSEL : LVR Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 28 - 30 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BGPEN : Band-gap Enable Control(Write Protect)\nBand-gap is the reference voltage of internal reference voltage. User must enable band-gap if want to enable internal 1.5, 1.8V or 2.5V reference voltage.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REGEN : Regulator Enable Control(Write Protect)\nEnable internal 1.5, 1.8V or 2.5V reference voltage.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SEL25 : Regulator Output Voltage Selection(Write Protect)\nSelect internal reference voltage level.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EXTMODE : Regulator External Mode(Write Protect)\nUsers can output regulator output voltage in VREF pin if EXT_MODE is high.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VREFTRIM : Internal Voltage Reference Trim(Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 8 - 11 (4 bit)
access : read-write

FASTWK : Fast Wake-up Control Bit (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LDOLVL : LDO Output Voltage Select(Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LPRMEN : Low-power Run Mode Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FMCLVEN : Flash Memory Low Voltage Mode Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BATDIV2EN : Battery Voltageg Divide 2 Enable Bit\nThis bit is used to enable/disable battery voltageg divider function.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACMPWK : ACMP Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with ACMP wake-up event. This flag is cleared when Power-down mode is entered.
bits : 0 - 0 (1 bit)
access : read-only

I2C1WK : I2C1 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with I2C1 wake-up event. This flag is cleared when Power-down mode is entered.
bits : 1 - 1 (1 bit)
access : read-only

I2C0WK : I2C0 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with I2C0 wake-up event. This flag is cleared when Power-down mode is entered.
bits : 2 - 2 (1 bit)
access : read-only

TMR3WK : TMR3 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested withTMR3 wake-up event. This flag is cleared when Power-down mode is entered.
bits : 3 - 3 (1 bit)
access : read-only

TMR2WK : TMR2 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested withTMR2 wake-up event. This flag is cleared when Power-down mode is entered.
bits : 4 - 4 (1 bit)
access : read-only

TMR1WK : TMR1 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested withTMR1 wake-up event. This flag is cleared when Power-down mode is entered.
bits : 5 - 5 (1 bit)
access : read-only

TMR0WK : TMR0 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested withTMR0 wake-up event. This flag is cleared when Power-down mode is entered.
bits : 6 - 6 (1 bit)
access : read-only

WDTWK : WDT Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with WDT wake-up event. This flag is cleared when Power-down mode is entered.
bits : 7 - 7 (1 bit)
access : read-only

BODWK : BOD Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with BOD wake-up event. This flag is cleared when Power-down mode is entered.
bits : 8 - 8 (1 bit)
access : read-only

SPI3WK : SPI3 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with SPI3 wake-up event. This flag is cleared when Power-down mode is entered.
bits : 9 - 9 (1 bit)
access : read-only

SPI2WK : SPI2 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with SPI2 wake-up event. This flag is cleared when Power-down mode is entered.
bits : 10 - 10 (1 bit)
access : read-only

SPI1WK : SPI1 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with SPI1 wake-up event. This flag is cleared when Power-down mode is entered.
bits : 11 - 11 (1 bit)
access : read-only

SPI0WK : SPI0 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with SPI0 wake-up event. This flag is cleared when Power-down mode is entered.
bits : 12 - 12 (1 bit)
access : read-only

UART1WK : UART1 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with UART1 wake-up event. This flag is cleared when Power-down mode is entered.
bits : 13 - 13 (1 bit)
access : read-only

UART0WK : UART0 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with UART0 wake-up event. This flag is cleared when Power-down mode is entered.
bits : 14 - 14 (1 bit)
access : read-only

RTCWK : RTC Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with a RTCalarm or tick time happened. This flag is cleared when Power-down mode is entered.
bits : 15 - 15 (1 bit)
access : read-only

GPIOWK : GPIO Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with GPIO wake-up event. This flag is cleared when Power-down mode is entered.
bits : 16 - 16 (1 bit)
access : read-only

CHIPRST : Chip One-shot Reset (Write Protect)\nSetting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload.\nAbout the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2\nNote:This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPURST : Processor Core One-shot Reset (Write Protect)\nSetting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles.\nNote:This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMARST : PDMA Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0 to release from reset state.\nNote:This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FREQSEL : Trim Frequency Selection\nThis field indicates the target frequency of 12 MHz internal high speed RC oscillator (HIRC0) auto trim.\nDuring auto trim operation, if clock error detected with CESTOPEN (SYS_IRC0TCTL[8]) is set to 1 or trim retry limitation count reached, this field will be cleared to 000 automatically.\nNote: HIRC0 auto trim cannot work normally inPower-down mode. These bits must be cleared before entering Power-down mode.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LOOPSEL : Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many 32.768 kHz clock.\nNote: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RETRYCNT : Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC0 trim value before the frequency of HIRC0 locked.\nOnce the HIRC0 locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of HIRC0 still doesn't lock, the auto trim operation will be disabled and FREQSEL (SYS_IRC0TCTL[1:0]) will be cleared to 00.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CESTOPEN : Clock Error Stop Enable Bit\nThis bit is used to control if stop the HIRC0 trim operation when 32.768 kHz clock error is detected.\nIf set this bit high and 32.768 kHz clock error detected, the status CLKERRIF (SYS_IRC0TISTS[2]) would be set high and HIRC0 trim operation was stopped. If this bit is low and 32.768 kHz clock error detected, the status CLKERRIF (SYS_IRC0TISTS[2]) would be set high and HIRC0 trim operation is continuously.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TFAILIEN : Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC0 trim value update limitation count reached and HIRC0 frequency still not locked on target frequency set by FREQSEL(SYS_IRC0TCTL[1:0]).\nIf this bit is high and TFAILIF(SYS_IRC0TSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC0 trim value update limitation count was reached.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKEIEN : Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1, and CLKERRIF(SYS_IRC0TSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FREQLOCK : HIRC0 Frequency Lock Status\nThis bit indicates the HIRC0 frequency is locked.\nThis is a status bit and doesn't trigger any interrupt.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TFAILIF : Trim Failure Interrupt Status\nThis bit indicates that HIRC0 trim value update limitation count reached and the HIRC0 clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_IRC0TCTL[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and TFAILIEN(SYS_IRC0TIEN[1]) is high, an interrupt will be triggered to notify that HIRC0 trim value update limitation count was reached. Write 1 to clear this to 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKERRIF : Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or internal high speed RC oscillator (HIRC0) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy\nOnce this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRC0TCTL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRC0TCTL[8]) is set to 1.\nIf this bit is set and CLKEIEN(SYS_IRC0TIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FREQSEL : Trim Frequency Selection\nThis field indicates the target frequency of 36 MHz internal high speed RC oscillator (HIRC1) auto trim.\nDuring auto trim operation, if clock error detected with CESTOPEN (SYS_IRC1TCTL[8]) is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.\nNote: HIRC1 auto trim cannot work normally inPower-down mode. These bits must be cleared before entering Power-down mode.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LOOPSEL : Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many 32.768 kHz clock.\nNote: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RETRYCNT : Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC1 trim value before the frequency of HIRC1 locked.\nOnce the HIRC1 locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of HIRC1 still doesn't lock, the auto trim operation will be disabled and FREQSEL (SYS_IRC1TCTL[1:0]) will be cleared to 00.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CESTOPEN : Clock Error Stop Enable Bit\nThis bit is used to control if stop the HIRC1 trim operation when 32.768 kHz clock error is detected.\nIf set this bit high and 32.768 kHz clock error detected, the status CLKERRIF (SYS_IRC1TISTS[2]) would be set high and HIRC1 trim operation was stopped. If this bit is low and 32.768 kHz clock error detected, the status CLKERRIF (SYS_IRC1TISTS[2]) would be set high and HIRC1 trim operation is continuously.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TFAILIEN : Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC1 trim value update limitation count reached and HIRC1 frequency still not locked on target frequency set by FREQSEL(SYS_IRC1TCTL[1:0]).\nIf this bit is high and TFAILIF(SYS_IRC1TSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC1 trim value update limitation count was reached.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKEIEN : Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1, and CLKERRIF(SYS_IRC1TSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FREQLOCK : HIRC1 Frequency Lock Status\nThis bit indicates the HIRC1 frequency is locked.\nThis is a status bit and doesn't trigger any interrupt.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TFAILIF : Trim Failure Interrupt Status\nThis bit indicates that HIRC1 trim value update limitation count reached and the HIRC1 clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_IRC1TCTL[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and TFAILIEN(SYS_IRC1TIEN[1]) is high, an interrupt will be triggered to notify that HIRC1 trim value update limitation count was reached. Write 1 to clear this to 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKERRIF : Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 36 MHz internal high speed RC oscillator (HIRC1) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy\nOnce this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRC1TCTL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRC1TCTL[8]) is set to 1.\nIf this bit is set and CLKEIEN(SYS_IRC1TIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FREQSEL : Trim Frequency Selection\nThis field indicates the target frequency of 4 MHz internal medium speed RC oscillator (MIRC) auto trim.\nDuring auto trim operation, if clock error detected with CESTOPEN (SYS_MIRCTCTL[8]) is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.\nNote:MIRC auto trim cannot work normally inPower downn mode. These bits must be cleared before entering Power-down mode.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LOOPSEL : Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many 32.768 kHz clock.\nNote: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RETRYCNT : Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the MIRC trim value before the frequency of MIRC locked.\nOnce the MIRC locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of MIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL (SYS_MIRCTCTL[1:0]) will be cleared to 00.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CESTOPEN : Clock Error Stop Enable Bit\nThis bit is used to control if stop the MIRC trim operation when 32.768 kHz clock error is detected.\nIf set this bit high and 32.768 kHz clock error detected, the status CLKERRIF (SYS_MIRCTISTS[2]) would be set high and MIRC trim operation was stopped. If this bit is low and 32.768 kHz clock error detected, the status CLKERRIF (SYS_MIRCTISTS[2]) would be set high and MIRC trim operation is continuously.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TFAILIEN : Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while MIRC trim value update limitation count reached and MIRC frequency still not locked on target frequency set by FREQSEL(SYS_MIRCTCTL[1:0]).\nIf this bit is high and TFAILIF(SYS_MIRCTSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that MIRC trim value update limitation count was reached.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKEIEN : Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1, and CLKERRIF(SYS_MIRCTSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.