\n

CLK

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x30 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected

Registers

CLK_PWRCTL (PWRCTL)

CLK_CLKSEL0 (CLKSEL0)

CLK_CLKSEL1 (CLKSEL1)

CLK_CLKSEL2 (CLKSEL2)

CLK_CLKDIV0 (CLKDIV0)

CLK_CLKDIV1 (CLKDIV1)

CLK_PLLCTL (PLLCTL)

CLK_CLKOCTL (CLKOCTL)

CLK_WKINTSTS (WKINTSTS)

CLK_APBDIV (APBDIV)

CLK_CLKDCTL (CLKDCTL)

CLK_CLKDIE (CLKDIE)

CLK_AHBCLK (AHBCLK)

CLK_CLKDSTS (CLKDSTS)

CLK_CDUPB (CDUPB)

CLK_CDLOWB (CDLOWB)

CLK_APBCLK (APBCLK)

CLK_STATUS (STATUS)


CLK_PWRCTL (PWRCTL)

System Power-down Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_PWRCTL CLK_PWRCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HXTEN LXTEN HIRC0EN LIRCEN PDWKDLY PDWKIEN PDEN HXTSLTYP HXTGAIN HIRC0FSEL HIRC0FSTOP HIRC1EN MIRCEN

HXTEN : HXT Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

4~32 MHz external high speed crystal (HXT) Disabled

#1 : 1

4~32 MHz external high speed crystal (HXT) Enabled

End of enumeration elements list.

LXTEN : LXT Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

32.768 kHz external lowspeed crystal (LXT) Disabled

#1 : 1

32.768 kHz external lowspeed crystal (LXT) Enabled

End of enumeration elements list.

HIRC0EN : HIRC0 Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

12~16 MHz internal high speed RC oscillator (HIRC0)Disabled

#1 : 1

12~16 MHz internal high speed RC oscillator (HIRC0)Enabled

End of enumeration elements list.

LIRCEN : LIRC Enable Bit(Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

10 kHz internal low speed RC oscillator (LIRC) Disabled

#1 : 1

10 kHz internal low speed RC oscillator (LIRC)Enabled

End of enumeration elements list.

PDWKDLY : Enable the Wake-up Delay Counter (Write Protect)\nWhen the chip wakes up from Power-down mode, the clock control will delay4096 clock cycles to wait system clock stable when chip works at 4~32 MHz external high speed crystal oscillator (HXT).\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock cycles delayDisabled

#1 : 1

Clock cycles delayEnabled

End of enumeration elements list.

PDWKIEN : Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)\nNote1: The interrupt (EINT0~1, GPIO,, UART0~1, WDT, ACMP01, BOD, RTC, TMR0~3, I2C0~1 or SPI0 ~3)will occur when PDWKIEN are high.\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Power-down mode wake-up interrupt Disabled

#1 : 1

Power-down mode wake-up interrupt Enabled

End of enumeration elements list.

PDEN : System Power-down Enable (Write Protect) When this bit is set to 1, Power-down mode is enabled and chip Power-down behavior will depend on the PDWTCPU bit. (a) If the PDWTCPU is 0, then the chip enters Power-down mode immediately after the PDEN bit set. (default) (b) if the PDWTCPU is 1, then the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode. When chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next Power-down. In Power-down mode, HXT and the HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode. In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Chip operating normally or chip in idle mode because of WFI command

#1 : 1

Chip enters Power-down mode instant or wait CPU sleep command WFI

End of enumeration elements list.

HXTSLTYP : HXT Mode Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

High frequency crystal loop back path Disabled. It is used for external oscillator

#1 : 1

High frequency crystal loop back path Enabled. It is used for external crystal

End of enumeration elements list.

HXTGAIN : HXT Gain Control Bit(Write Protect)\nGain control is used to enlarge the gain of crystal to make sure crystal wok normally. If gain control is enabled, crystal will consume more power than gain control off.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 10 - 12 (3 bit)
access : read-write

Enumeration:

#000 : 0

HXT frequency is lower than from 4 MHz

#001 : 1

HXT frequency is from 4 MHz to 8 MHz

#010 : 2

HXT frequency is from 8 MHz to 12 MHz

#011 : 3

HXT frequency is from 12 MHz to 16 MHz

#100 : 4

HXT frequency is from 16 MHz to 24 MHz

#101 : 5

HXT frequency is from 24 MHz to 32 MHz

#110 : 6

HXT frequency is from 32 MHz to 36 MHz

#111 : 7

HXT frequency is higher than 36 MHz

End of enumeration elements list.

HIRC0FSEL : HIRC0 Output Frequency Select Bit
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

HIRC0 will output 12MHz clock

#1 : 1

HIRC0 will output 16MHz Clock

End of enumeration elements list.

HIRC0FSTOP : HIRC0 Stop Output When Frequency Changes (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

HIRC0 will continue to output when HIRC frequency changes

#1 : 1

HIRC0will suppress to output during first 16 clocks when HIRC frequency change

End of enumeration elements list.

HIRC1EN : HIRC1 Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

36 MHz internal high speed RC oscillator (HIRC1)Disabled

#1 : 1

36 MHz internal high speed RC oscillator (HIRC1)Enabled

End of enumeration elements list.

MIRCEN : MIRC Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

4 MHz internal medium speed RC oscillator (MIRC)Disabled

#1 : 1

4 MHz internal medium speed RC oscillator (MIRC)Enabled

End of enumeration elements list.


CLK_CLKSEL0 (CLKSEL0)

Clock Source Select Control Register 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKSEL0 CLK_CLKSEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HCLKSEL HIRCSEL ISPSEL

HCLKSEL : HCLK Clock Source Selection(Write Protect)\nBefore clock switching, the related clock sources (both pre-select and new-select) must be turned on.\nNote:This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from HXT

#001 : 1

Clock source from LXT

#010 : 2

Clock source from PLL

#011 : 3

Clock source from LIRC

#100 : 4

Clock source from HIRC1 or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting

End of enumeration elements list.

HIRCSEL : HIRC Source Selection
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock source from HIRC0 (12~16MHz)

#1 : 1

Clock source from HIRC1 (36MHz)

End of enumeration elements list.

ISPSEL : ISP Clock Source Selection
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock source from HIRC1 or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting

#1 : 1

Clock source from MIRC

End of enumeration elements list.


CLK_CLKSEL1 (CLKSEL1)

Clock Source Select Control Register 1
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKSEL1 CLK_CLKSEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART0SEL PWM0SEL TMR0SEL TMR1SEL ADCSEL SPI0SEL SPI2SEL WDTSEL WWDTSEL

UART0SEL : UART0 Clock Source Selection
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from 4~32 MHz external high speed crystal oscillator (HXT)

#001 : 1

Clock source from 32.768 kHz external low speed crystal oscillator (LXT)

#010 : 2

Clock source from PLL

#011 : 3

Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting

End of enumeration elements list.

PWM0SEL : PWM0 Clock Source Selection
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock source from PLL

#1 : 1

Clock source from PCLK0

End of enumeration elements list.

TMR0SEL : Timer0 Clock Source Selection
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from 4~32 MHz external high speed crystal oscillator (HXT)

#001 : 1

Clock source from 32.768 kHz external low speed crystal oscillator (LXT)

#010 : 2

Clock source from 10 kHz internal low speed RC oscillator (LIRC)

#011 : 3

Clock source from external clock pin

#100 : 4

Clock source from36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting

#101 : 5

Clock source from 4 MHz internal medium speed RC oscillator (MIRC)

End of enumeration elements list.

TMR1SEL : Timer1 Clock Source Selection
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from 4~32 MHz external high speed crystal oscillator (HXT)

#001 : 1

Clock source from 32.768 kHz external low speed crystal oscillator (LXT)

#010 : 2

Clock source from 10 kHz internal low speed RC oscillator (LIRC)

#011 : 3

Clock source from external clock pin

#100 : 4

Clock source from36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting

#101 : 5

Clock source from 4 MHz internal medium speed RC oscillator (MIRC)

End of enumeration elements list.

ADCSEL : ADC Clock Source Selection
bits : 19 - 21 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from 4~32 MHz external high speed crystal oscillator (HXT)

#001 : 1

Clock source from 32.768 kHz external low speed crystal oscillator (LXT)

#010 : 2

Clock source from PLL

#011 : 3

Clock source from36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting

#100 : 4

Clock source from 4 MHz internal medium speed RC oscillator (MIRC)

End of enumeration elements list.

SPI0SEL : SPI0 Clock Source Selection
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from PLL

#01 : 1

Clock source from HCLK

#10 : 2

Clock source from 4~32 MHz external high speed crystal oscillator (HXT)

#11 : 3

Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting

End of enumeration elements list.

SPI2SEL : SPI2 Clock Source Selection
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from PLL

#01 : 1

Clock source from HCLK

#10 : 2

Clock source from 4~32 MHz external high speed crystal oscillator (HXT)

#11 : 3

Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting

End of enumeration elements list.

WDTSEL : WDT Clock Source Selection
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

#00 : 0

reserved

#01 : 1

Clock source from LXT

#10 : 2

Clock source from HCLK/2048

#11 : 3

Clock source from LIRC

End of enumeration elements list.

WWDTSEL : WDT Clock Source Selection
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

#00 : 0

reserved

#01 : 1

reserved

#10 : 2

Clock source from HCLK/2048

#11 : 3

Clock source from LIRC

End of enumeration elements list.


CLK_CLKSEL2 (CLKSEL2)

Clock Source Select Control Register 2
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKSEL2 CLK_CLKSEL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART1SEL CLKOSEL DSRCSEL TMR2SEL TMR3SEL SC0SEL SC1SEL SPI1SEL SPI3SEL

UART1SEL : UART1 Clock Source Selection
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from 4~32 MHz external high speed crystal oscillator (HXT)

#001 : 1

Clock source from 32.768 kHz external low speed crystal oscillator (LXT)

#010 : 2

Clock source from PLL

#011 : 3

Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting

End of enumeration elements list.

CLKOSEL : Clock Divider Clock Source Selection
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from 4~32 MHz external high speed crystal oscillator (HXT)

#001 : 1

Clock source from 32.768 kHz external low speed crystal oscillator (LXT)

#010 : 2

Clock source from HCLK

#011 : 3

Clock source from36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting

End of enumeration elements list.

DSRCSEL : DSRC Clock Source Selection
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock source from 4 MHz internal medium speed RC oscillator (MIRC)

#1 : 1

Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting

End of enumeration elements list.

TMR2SEL : Timer2 Clock Source Selection
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from 4~32 MHz external high speed crystal oscillator (HXT)

#001 : 1

Clock source from 32.768 kHz external low speed crystal oscillator (LXT)

#010 : 2

Clock source from 10 kHz internal low speed RC oscillator (LIRC)

#011 : 3

Clock source from external clock pin

#100 : 4

Clock source from36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting

#101 : 5

Clock source from 4 MHz internal medium speed RC oscillator (MIRC)

End of enumeration elements list.

TMR3SEL : Timer3 Clock Source Selection
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from 4~32 MHz external high speed crystal oscillator (HXT)

#001 : 1

Clock source from 32.768 kHz external low speed crystal oscillator (LXT)

#010 : 2

Clock source from 10 kHz internal low speed RC oscillator (LIRC)

#011 : 3

Clock source from external clock pin

#100 : 4

Clock source from36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting

#101 : 5

Clock source from 4 MHz internal medium speed RC oscillator (MIRC)

End of enumeration elements list.

SC0SEL : SC0 Clock Source Selection
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from 4~32 MHz external high speed crystal oscillator (HXT)

#001 : 1

Clock source from PLL

#010 : 2

Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting

#011 : 3

Clock source from 4 MHz internal medium speed RC oscillator (MIRC)

End of enumeration elements list.

SC1SEL : SC1 Clock Source Selection
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from 4~32 MHz external high speed crystal oscillator (HXT)

#001 : 1

Clock source from PLL

#010 : 2

Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting

#011 : 3

Clock source from 4 MHz internal medium speed RC oscillator (MIRC)

End of enumeration elements list.

SPI1SEL : SPI1 Clock Source Selection
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from PLL

#01 : 1

Clock source from HCLK

#10 : 2

Clock source from 4~32 MHz external high speed crystal oscillator (HXT)

#11 : 3

Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting

End of enumeration elements list.

SPI3SEL : SPI3 Clock Source Selection
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from PLL

#01 : 1

Clock source from HCLK

#10 : 2

Clock source from 4~32 MHz external high speed crystal oscillator (HXT)

#11 : 3

Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting

End of enumeration elements list.


CLK_CLKDIV0 (CLKDIV0)

Clock Divider Number Register 0
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKDIV0 CLK_CLKDIV0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HCLKDIV UART0DIV UART1DIV ADCDIV SC0DIV

HCLKDIV : HCLK Clock Divide Number From HCLK Clock Source
bits : 0 - 3 (4 bit)
access : read-write

UART0DIV : UART0Clock Divide Number From UART Clock Source
bits : 8 - 11 (4 bit)
access : read-write

UART1DIV : UART1Clock Divide Number From UART Clock Source
bits : 12 - 15 (4 bit)
access : read-write

ADCDIV : ADC Clock Divide Number From ADC Clock Source
bits : 16 - 23 (8 bit)
access : read-write

SC0DIV : SC0Clock Divide Number From SC0Clock Source
bits : 28 - 31 (4 bit)
access : read-write


CLK_CLKDIV1 (CLKDIV1)

Clock Divider Number Register 1
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKDIV1 CLK_CLKDIV1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SC1DIV TMR0DIV TMR1DIV TMR2DIV TMR3DIV DSRCDIV

SC1DIV : SC 1Clock Divide Number From SC 1Clock Source
bits : 0 - 3 (4 bit)
access : read-write

TMR0DIV : Timer0Clock Divide Number From Timer0Clock Source
bits : 8 - 11 (4 bit)
access : read-write

TMR1DIV : Timer1Clock Divide Number From Timer1Clock Source
bits : 12 - 15 (4 bit)
access : read-write

TMR2DIV : Timer2Clock Divide Number From Timer2Clock Source
bits : 16 - 19 (4 bit)
access : read-write

TMR3DIV : Timer3Clock Divide Number From Timer3Clock Source
bits : 20 - 23 (4 bit)
access : read-write

DSRCDIV : DSRC Clock Divide Number From DSRCClock Source
bits : 24 - 28 (5 bit)
access : read-write


CLK_PLLCTL (PLLCTL)

PLL Control Register
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_PLLCTL CLK_PLLCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLLMLP INDIV STBCNT PD PLLSRC

PLLMLP : PLL Multiple\n000000: Reserved\n000001: X1\n000010: X2\n000011: X3\n000100: X4\n...\n010000:X16\n...\n100000: X32\n100100: X36\n0thers: Reserved \nPLL output frequency: PLL input frequency * PLLMLP.\nPLL output frequency range: 16MHz ~ 36MHz
bits : 0 - 5 (6 bit)
access : read-write

INDIV : PLL Input Source Divider \nPLL input clock frequency range: 0.8MHz ~ 2MHz
bits : 8 - 13 (6 bit)
access : read-write

STBCNT : PLL Stable Time Selection
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

#00 : 0

100 cycle time of input clock source

#01 : 1

120 cycle time of input clock source

#10 : 2

180 cycle time of input clock source

#11 : 3

240 cycle time of input clock source

End of enumeration elements list.

PD : Power-down Mode If set the PDEN bit 1 in CLK_PWRCTL register, the PLL will enter Power-down mode too
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL is in normal mode

#1 : 1

PLL is in power-down mode (default)

End of enumeration elements list.

PLLSRC : PLL Source Clock Select
bits : 17 - 18 (2 bit)
access : read-write

Enumeration:

#00 : 0

PLL source clock from HXT

#01 : 1

PLL source clock from HIRC0 or HIRC1

#10 : 2

PLL source clock from MIRC

#11 : 3

reserved

End of enumeration elements list.


CLK_CLKOCTL (CLKOCTL)

Clock Output Control Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKOCTL CLK_CLKOCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FREQSEL CLKOEN DIV1EN

FREQSEL : Clock Output Frequency Selection\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FREQSEL[3:0].
bits : 0 - 3 (4 bit)
access : read-write

CLKOEN : Clock Output Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock Output function Disabled

#1 : 1

Clock Output function Enabled

End of enumeration elements list.

DIV1EN : Clock Output Divide One Enable Bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock Output will output clock with source frequency divided by FREQSEL

#1 : 1

Clock Output will output clock with source frequency

End of enumeration elements list.


CLK_WKINTSTS (WKINTSTS)

Wake-up Interrupt Status
address_offset : 0x30 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CLK_WKINTSTS CLK_WKINTSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDWKIF

PDWKIF : Wake-up Interrupt Status in Chip Power-down Mode\nThis bit indicates that some event resumes chip from Power-down mode\nThe status is set if external interrupts, UART, GPIO, RTC, USB, SPI, Timer, WDT, and BOD wake-up occurred.\nWrite 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-only


CLK_APBDIV (APBDIV)

APB Clock Divider
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_APBDIV CLK_APBDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APB0DIV APB1DIV

APB0DIV : APB0 Clock Divider\nAPB0 PCLK0 can be divided from HCLK.
bits : 0 - 2 (3 bit)
access : read-write

APB1DIV : APB1 Clock Divider\nAPB1 PCLK1 can be divided from HCLK.
bits : 4 - 6 (3 bit)
access : read-write


CLK_CLKDCTL (CLKDCTL)

Clock Fail Detector Control Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKDCTL CLK_CLKDCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HXTFDEN LXTFDEN HXTFQDEN

HXTFDEN : HXT Clock Fail Detector Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

4~32 MHz external high speed crystal oscillator (HXT) clock fail detector Disabled

#1 : 1

4~32 MHz external high speed crystal oscillator (HXT) clock fail detector Enabled

End of enumeration elements list.

LXTFDEN : LXT Clock Fail Detector Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Disabled

#1 : 1

32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Enabled

End of enumeration elements list.

HXTFQDEN : HXT Clock Frequency Monitor Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

4~32 MHz external high speed crystal oscillator (HXT) clock frequency monitor Disabled

#1 : 1

4~32 MHz external high speed crystal oscillator (HXT) clock frequency monitor Enabled

End of enumeration elements list.


CLK_CLKDIE (CLKDIE)

Clock Fail Detector Interrupt Enable Register
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKDIE CLK_CLKDIE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HXTFIEN LXTFIEN HXTFQIEN

HXTFIEN : HXT Clock Fail Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

4~32 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled

#1 : 1

4~32 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled

End of enumeration elements list.

LXTFIEN : LXT Clock Fail Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled

#1 : 1

32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled

End of enumeration elements list.

HXTFQIEN : HXT Clock Frequency Monitor Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

4~32 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Disabled

#1 : 1

4~32 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Enabled

End of enumeration elements list.


CLK_AHBCLK (AHBCLK)

AHB Devices Clock Enable Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_AHBCLK CLK_AHBCLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOCKEN PDMACKEN ISPCKEN SRAMCKEN STCKEN

GPIOCKEN : GPIO Controller Clock Enable Control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO peripheral clock Disabled

#1 : 1

GPIO peripheral clock Enabled

End of enumeration elements list.

PDMACKEN : PDMA Controller Clock Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

PDMA peripheral clock Disabled

#1 : 1

PDMA peripheral clock Enabled

End of enumeration elements list.

ISPCKEN : Flash ISP Controller Clock Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Flash ISP peripheral clock Disabled

#1 : 1

Flash ISP peripheral clock Enabled

End of enumeration elements list.

SRAMCKEN : SRAM Controller Clock Enable Control Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

SRAM peripheral clock Disabled

#1 : 1

SRAM peripheral clock Enabled

End of enumeration elements list.

STCKEN : System Tick Clock Enable Control Bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

System Tick Clock Disabled

#1 : 1

System Tick Clock Enabled

End of enumeration elements list.


CLK_CLKDSTS (CLKDSTS)

Clock Fail Detector Status Register
address_offset : 0x40 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKDSTS CLK_CLKDSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HXTFIF LXTFIF HXTFQIF

HXTFIF : HXT Clock Fail Interrupt Flag\nNote: Write 1 to clear the bit to 0.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

4~32 MHz external high speed crystal oscillator (HXT) clock is normal

#1 : 1

4~32 MHz external high speed crystal oscillator (HXT) clock stops

End of enumeration elements list.

LXTFIF : LXT Clock Fail Interrupt Flag\nNote: Write 1 to clear the bit to 0.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

32.768 kHz external low speed crystal oscillator (LXT) clock is normal

#1 : 1

32.768 kHz external low speed crystal oscillator (LXT) stops

End of enumeration elements list.

HXTFQIF : HXT Clock Frequency Monitor Interrupt Flag\nNote: Write 1 to clear the bit to 0.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

4~32 MHz external high speed crystal oscillator (HXT) clock is normal

#1 : 1

4~32 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal

End of enumeration elements list.


CLK_CDUPB (CDUPB)

Clock Frequency Detector Upper Boundary Register
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CDUPB CLK_CDUPB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPERBD

UPERBD : HXT Clock Frequency Detector Upper Boundary\nThe bits define the high value of frequency monitor window.\nWhen HXT frequency monitor value higher than this register, the HXT frequency detect fail interrupt flag will set to 1.
bits : 0 - 10 (11 bit)
access : read-write


CLK_CDLOWB (CDLOWB)

Clock Frequency Detector Lower Boundary Register
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CDLOWB CLK_CDLOWB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOWERBD

LOWERBD : HXT Clock Frequency Detector Lower Boundary\nThe bits define the low value of frequency monitor window.\nWhen HXT frequency monitor value lower than this register, the HXT frequency detect fail interrupt flag will set to 1.
bits : 0 - 10 (11 bit)
access : read-write


CLK_APBCLK (APBCLK)

APB Devices Clock Enable Control Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_APBCLK CLK_APBCLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTCKEN RTCCKEN TMR0CKEN TMR1CKEN TMR2CKEN TMR3CKEN CLKOCKEN DSRCCKEN I2C0CKEN I2C1CKEN ACMP0CKEN SPI0CKEN SPI1CKEN SPI2CKEN SPI3CKEN UART0CKEN UART1CKEN PWM0CKEN ADCCKEN SC0CKEN SC1CKEN

WDTCKEN : Watchdog Timer Clock Enable Control \nThis is a protected register. Please refer to open lock sequence to program it.\nThis bit is used to control the WDT APB clock only, The WDT engine Clock Source is from LIRC.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Watchdog Timer Clock Disabled

#1 : 1

Watchdog Timer Clock Enabled

End of enumeration elements list.

RTCCKEN : Real-time-clock Clock Enable Control \nThis bit is used to control the RTC APB clock only, The RTC engine Clock Source is from LXT.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Real-time-clock Clock Disabled

#1 : 1

Real-time-clock Clock Enabled

End of enumeration elements list.

TMR0CKEN : Timer0 Clock Enable Control
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer0 Clock Disabled

#1 : 1

Timer0 Clock Enabled

End of enumeration elements list.

TMR1CKEN : Timer1 Clock Enable Control
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer1 Clock Disabled

#1 : 1

Timer1 Clock Enabled

End of enumeration elements list.

TMR2CKEN : Timer2 Clock Enable Control
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer2 Clock Disabled

#1 : 1

Timer2 Clock Enabled

End of enumeration elements list.

TMR3CKEN : Timer3 Clock Enable Control
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer3 Clock Disabled

#1 : 1

Timer3 Clock Enabled

End of enumeration elements list.

CLKOCKEN : ClocK Output Clock Enable Control
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock Output Clock Disabled

#1 : 1

Clock Output Clock Enabled

End of enumeration elements list.

DSRCCKEN : DSRC Clock Enable Control
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

DSRC Clock Disabled

#1 : 1

DSRC Clock Enabled

End of enumeration elements list.

I2C0CKEN : I2C0 Clock Enable Control
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C0 Clock Disabled

#1 : 1

I2C0 Clock Enabled

End of enumeration elements list.

I2C1CKEN : I2C1 Clock Enable Control
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C1 Clock Disabled

#1 : 1

I2C1 Clock Enabled

End of enumeration elements list.

ACMP0CKEN : ACMP0 Clock Enable Control
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

ACMP0 Clock Disabled

#1 : 1

ACMP0 Clock Enabled

End of enumeration elements list.

SPI0CKEN : SPI0 Clock Enable Control
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI0 Clock Disabled

#1 : 1

SPI0 Clock Enabled

End of enumeration elements list.

SPI1CKEN : SPI1 Clock Enable Control
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI1 Clock Disabled

#1 : 1

SPI1 Clock Enabled

End of enumeration elements list.

SPI2CKEN : SPI2 Clock Enable Control
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI2 Clock Disabled

#1 : 1

SPI2 Clock Enabled

End of enumeration elements list.

SPI3CKEN : SPI3 Clock Enable Control
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI3 Clock Disabled

#1 : 1

SPI3 Clock Enabled

End of enumeration elements list.

UART0CKEN : UART0 Clock Enable Control
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART0 Clock Disabled

#1 : 1

UART0 Clock Enabled

End of enumeration elements list.

UART1CKEN : UART1 Clock Enable Control
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART1 Clock Disabled

#1 : 1

UART1 Clock Enabled

End of enumeration elements list.

PWM0CKEN : PWM0 Clock Enable Control
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0 Clock Disabled

#1 : 1

PWM0 Clock Enabled

End of enumeration elements list.

ADCCKEN : Analog-digital-converter (ADC) Clock Enable Control
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

ADC Clock Disabled

#1 : 1

ADC Clock Enabled

End of enumeration elements list.

SC0CKEN : SmartCard 0 Clock Enable Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

SmartCard 0 Clock Disabled

#1 : 1

SmartCard 0 Clock Enabled

End of enumeration elements list.

SC1CKEN : SmartCard 1 Clock Enable Control
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

SmartCard 1 Clock Disabled

#1 : 1

SmartCard 1 Clock Enabled

End of enumeration elements list.


CLK_STATUS (STATUS)

Clock status monitor Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CLK_STATUS CLK_STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HXTSTB LXTSTB PLLSTB LIRCSTB HIRC0STB HIRC1STB MIRCSTB CLKSFAIL

HXTSTB : HXTClock Source Stable Flag(Read Only)
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

4~36 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled

#1 : 1

4~36 MHz external high speed crystal oscillator (HXT)clock is stable and enabled

End of enumeration elements list.

LXTSTB : LXTClock Source Stable Flag(Read Only)
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled

#1 : 1

32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled

End of enumeration elements list.

PLLSTB : Internal PLL Clock Source Stable Flag(Read Only)
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal PLL clock is not stable or disabled

#1 : 1

Internal PLL clock is stable and enabled

End of enumeration elements list.

LIRCSTB : LIRCClock Source Stable Flag(Read Only)
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

#0 : 0

10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled

#1 : 1

10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled

End of enumeration elements list.

HIRC0STB : HIRC0 Clock Source Stable Flag (Read Only)
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

12~16 MHz internal high speed RC oscillator (HIRC0) clock is not stable or disabled

#1 : 1

12~16 MHz internal high speed RC oscillator (HIRC0) clock is stable and enabled

End of enumeration elements list.

HIRC1STB : HIRCClock Source Stable Flag(Read Only)
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

#0 : 0

36 MHz internal high speed RC oscillator (HIRC1) clock is not stable or disabled

#1 : 1

36 MHz internal high speed RC oscillator (HIRC1) clock is stable and enabled

End of enumeration elements list.

MIRCSTB : MIRCClock Source Stable Flag(Read Only)
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

4 MHz internal medium speed RC oscillator (MIRC) clock is not stable or disabled

#1 : 1

4 MHz internal medium speed RC oscillator (MIRC) clock is stable and enabled

End of enumeration elements list.

CLKSFAIL : Clock Switching Fail Flag(Read Only)\nThis bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

#0 : 0

Clock switching success

#1 : 1

Clock switching failure

End of enumeration elements list.



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