\n

PDMA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x14 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PDMA_CTLn

PDMA_CSAn

PDMA_CDAn

PDMA_CCNTn

PDMA_INTENn

PDMA_INTSTSn

PDMA_TOCn

PDMA_SAn

PDMA_DAn

PDMA_CNTn


PDMA_CTLn

PDMA Channel n Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_CTLn PDMA_CTLn read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHEN SWRST SASEL DASEL TOUTEN TXWIDTH TRIGEN

CHEN : PDMA Channel Enable Bit\nSetting this bit to 1 enables PDMA operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.
bits : 0 - 0 (1 bit)
access : read-write

SWRST : Software Engine Reset
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Reset the internal state machine, pointers and internal buffer. The contents of all control registers will not be cleared. This bit will be automatically cleared after few clock cycles

End of enumeration elements list.

SASEL : Transfer Source Address Direction Selection
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 0

Transfer Source address is incremented successively

#01 : 1

Reserved

#10 : 2

Transfer Source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)

#11 : 3

Transfer Source address is wrap around (When the PDMA_CCNT is equal to 0, the PDMA_CSA and PDMA_CCNT registers will be updated by PDMA_SA and PDMA_CNT automatically. PDMA will start another transfer without user trigger until CHEN disabled. When the CHEN is disabled, the PDMA will complete the active transfer but the remained data which in the PDMA buffer will not transfer to destination address)

End of enumeration elements list.

DASEL : Transfer Destination Address Direction Selection
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 0

Transfer Destination address is incremented successively

#01 : 1

Reserved

#10 : 2

Transfer Destination address is fixed. (This feature can be used when data transferred from multiple sources to a single destination)

#11 : 3

Transfer Destination address is wrapped around (When the PDMA_CCNT is equal to 0, the PDMA_CDA and PDMA_CCNT registers will be updated by PDMA_DA and PDMA_CNT automatically. PDMA will start another transfer without user trigger until CHEN disabled. When the CHEN is disabled, the PDMA will complete the active transfer but the remained data which in the PDMA buffer will not transfer to destination address)

End of enumeration elements list.

TOUTEN : Time-out Enable Bit
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

PDMA internal counter Disabled

#1 : 1

PDMA internal counter Enabled

End of enumeration elements list.

TXWIDTH : Transfer Width Selection\nThis field is used for transfer width.
bits : 19 - 20 (2 bit)
access : read-write

Enumeration:

#00 : 0

One word (32-bit) is transferred for every PDMA operation

#01 : 1

One byte (8-bit) is transferred for every PDMA operation

#10 : 2

One half-word (16-bit) is transferred for every PDMA operation

#11 : 3

Reserved

End of enumeration elements list.

TRIGEN : Trigger Enable Bit \nNote1: When PDMA transfer completed, this bit will be cleared automatically.\nNote2: If the bus error occurs, all PDMA transfer will be stopped. User must reset all PDMA channels, and then trigger again.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

PDMA data transfer Enabled

End of enumeration elements list.


PDMA_CSAn

PDMA Channel n Current Source Address Register
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PDMA_CSAn PDMA_CSAn read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSA

CSA : PDMA Current Source Address Bits (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred.
bits : 0 - 31 (32 bit)
access : read-only


PDMA_CDAn

PDMA Channel n Current Destination Address Register
address_offset : 0x18 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PDMA_CDAn PDMA_CDAn read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CDA

CDA : PDMA Current Destination Address Bits (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred.
bits : 0 - 31 (32 bit)
access : read-only


PDMA_CCNTn

PDMA Channel n Current Transfer Count Register
address_offset : 0x1C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PDMA_CCNTn PDMA_CCNTn read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCNT

CCNT : PDMA Current Count Bits (Read Only)\nThis field indicates the current remained transfer count of PDMA.
bits : 0 - 15 (16 bit)
access : read-only


PDMA_INTENn

PDMA Channel n Interrupt Enable Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_INTENn PDMA_INTENn read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TABTIEN TDIEN TOUTIEN PCNTIEN

TABTIEN : PDMA Read/Write Target Abort Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Target abort interrupt Disabled during PDMA transfer

#1 : 1

Target abort interrupt Enabled during PDMA transfer

End of enumeration elements list.

TDIEN : PDMA Transfer Done Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt Disabled when PDMA transfer is done

#1 : 1

Interrupt Enabled when PDMA transfer is done

End of enumeration elements list.

TOUTIEN : Time-out Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Time-out interrupt Disabled

#1 : 1

Time-out interrupt Enabled

End of enumeration elements list.

PCNTIEN : Periodic Count Interrupt Enable Bit\nThis field indicates how many data transferred to generate interrupt periodically.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Periodic transfer count interrupt Disabled

#1 : 1

Periodic transfer count interrupt Enabled

End of enumeration elements list.


PDMA_INTSTSn

PDMA Channel n Interrupt Status Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_INTSTSn PDMA_INTSTSn read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TABTIF TDIF TOUTIF PCNTIF

TABTIF : PDMA Read/Write Target Abort Interrupt Status Flag Note1: This bit is cleared by writing 1 to it. Note2: This bit indicates bus master received error response or not, if bus master received error response, it means that PDMA transfer data from an invalid address or to an invalid adress .At this time target abort is happened..PDMA controller will stop transfer and respond this event to user then go to IDLE state. When target abort occurred, user must reset PDMA controller, and then transfer those data again.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No bus ERROR response received

#1 : 1

Bus ERROR response received

End of enumeration elements list.

TDIF : Transfer Done Interrupt Status Flag This bit indicates that PDMA has finished all transfer. Note: This bit is cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Not finished yet

#1 : 1

Done

End of enumeration elements list.

TOUTIF : Time-out Interrupt Status Flag This flag indicated that PDMA has waited peripheral request for a period defined by PDMA_TOC. Note: This bit is cleared by writing 1 to it.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

No time-out flag

#1 : 1

Time-out flag

End of enumeration elements list.

PCNTIF : Periodic Count Interrupt Status Flag Note: This bit is cleared by writing 1 to it.
bits : 8 - 8 (1 bit)
access : read-write


PDMA_TOCn

PDMA Channel n Time-out Counter Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_TOCn PDMA_TOCn read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOC TPSC

TOC : PDMA Time-out Period Counter
bits : 0 - 15 (16 bit)
access : read-write

TPSC : PDMA Time-out Counter Clock Source Prescaler
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#000 : 0

PDMA time-out clock source is HCLK/28

#001 : 1

PDMA time-out clock source is HCLK/29

#010 : 2

PDMA time-out clock source is HCLK/210

#011 : 3

PDMA time-out clock source is HCLK/211

#100 : 4

PDMA time-out clock source is HCLK/212

#101 : 5

PDMA time-out clock source is HCLK/213

#110 : 6

PDMA time-out clock source is HCLK/214

#111 : 7

PDMA time-out clock source is HCLK/215

End of enumeration elements list.


PDMA_SAn

PDMA Channel n Source Address Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_SAn PDMA_SAn read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : PDMA Transfer Source Address Bits\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment.
bits : 0 - 31 (32 bit)
access : read-write


PDMA_DAn

PDMA Channel n Destination Address Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DAn PDMA_DAn read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : PDMA Transfer Destination Address Bits\nThis field indicates a 32-bit destination address of PDMA.\nNote: The Destination address must be word alignment.
bits : 0 - 31 (32 bit)
access : read-write


PDMA_CNTn

PDMA Channel n Transfer Count Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_CNTn PDMA_CNTn read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCNT PCNTITH

TCNT : PDMA Transfer Count Bits\nThis field indicates a 16-bit transfer count number of PDMA.
bits : 0 - 15 (16 bit)
access : read-write

PCNTITH : PDMA Periodic Count Interrupt Threshold\nThis field indicates how many data transferred to generate periodic interrupt\nNote: write 0 to this field to disable this function.
bits : 16 - 31 (16 bit)
access : read-write



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