\n

PDMA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PDMA_GCTL

PDMA_REQSEL0

PDMA_REQSEL1

PDMA_GINTSTS


PDMA_GCTL

PDMA Global Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_GCTL PDMA_GCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CKEN1 CKEN2 CKEN3 CKEN4 CKENCRC

CKEN1 : PDMA Controller Channel 1 Clock Enable Bit
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

PDMA channel 1 clock Disabled

#1 : 1

PDMA channel 1 clock Enabled

End of enumeration elements list.

CKEN2 : PDMA Controller Channel 2 Clock Enable Bit
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

PDMA channel 2 clock Disabled

#1 : 1

PDMA channel 2 clock Enabled

End of enumeration elements list.

CKEN3 : PDMA Controller Channel 3 Clock Enable Bit
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

PDMA channel 3 clock Disabled

#1 : 1

PDMA channel 3 clock Enabled

End of enumeration elements list.

CKEN4 : PDMA Controller Channel 4 Clock Enable Bit
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

PDMA channel 4 clock Disabled

#1 : 1

PDMA channel 4 clock Enabled

End of enumeration elements list.

CKENCRC : CRC Controller Clock Enable Bit
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

CRC channel clock Disabled

#1 : 1

CRC channel clock Enabled

End of enumeration elements list.


PDMA_REQSEL0

PDMA Request Source Select Register 0
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_REQSEL0 PDMA_REQSEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REQSRC1 REQSRC2 REQSRC3

REQSRC1 : Channel 1 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 1. User can configure the peripheral by setting REQSRC1
bits : 8 - 12 (5 bit)
access : read-write

Enumeration:

#00000 : 0

Connect to SPI0_TX

#00001 : 1

Connect to SPI1_TX

#00010 : 2

Connect to UART0_TX

#00011 : 3

Connect to UART1_TX

#00100 : 4

Reserved

#00101 : 5

Connect to SPI3_TX

#00110 : 6

Reserved

#00111 : 7

Reserved

#01000 : 8

Connect to SPI2_TX

#01001 : 9

Connect to TMR0

#01010 : 10

Connect to TMR1

#01011 : 11

Connect to TMR2

#01100 : 12

Connect to TMR3

#10000 : 16

Connect to SPI0_RX

#10001 : 17

Connect to SPI1_RX

#10010 : 18

Connect to UART0_RX

#10011 : 19

Connect to UART1_RX

#10100 : 20

Reserved

#10101 : 21

Connect to SPI3_RX

#10110 : 22

Connect to ADC

#10111 : 23

Reserved

#11000 : 24

Connect to SPI2_RX

#11001 : 25

Reserved

#11010 : 26

Reserved

#11011 : 27

Reserved

#11100 : 28

Reserved

End of enumeration elements list.

REQSRC2 : Channel 2 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 2. User can configure the peripheral setting by REQSRC2. \nNote: The channel configuration is the same as REQSRC1 field. Please refer to the explanation of REQSRC1.
bits : 16 - 20 (5 bit)
access : read-write

REQSRC3 : Channel 3 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 3. User can configure the peripheral setting by REQSRC3. \nNote: The channel configuration is the same as REQSRC1 field. Please refer to the explanation of REQSRC1.
bits : 24 - 28 (5 bit)
access : read-write


PDMA_REQSEL1

PDMA Request Source Select Register 1
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_REQSEL1 PDMA_REQSEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REQSRC4

REQSRC4 : Channel 4 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 4. User can configure the peripheral setting by REQSRC4. \nNote: The channel configuration is the same as REQSRC1 field. Please refer to the explanation of REQSRC1.
bits : 0 - 4 (5 bit)
access : read-write


PDMA_GINTSTS

PDMA Global Interrupt Status Register
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PDMA_GINTSTS PDMA_GINTSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IF1 IF2 IF3 IF4 IFCRC

IF1 : PDMA Channel 1 Interrupt Status (Read Only)\nThis bit indicates the interrupt status of PDMA channel 1.
bits : 1 - 1 (1 bit)
access : read-only

IF2 : PDMA Channel 2 Interrupt Status Flag of (Read Only)\nThis bit indicates the interrupt status of PDMA channel 2.
bits : 2 - 2 (1 bit)
access : read-only

IF3 : PDMA Channel 3 Interrupt Status (Read Only)\nThis bit indicates the interrupt status of PDMA channel 3.
bits : 3 - 3 (1 bit)
access : read-only

IF4 : PDMA Channel 4 Interrupt Status Flag (Read Only)\nThis bit indicates the interrupt status of PDMA channel 4.
bits : 4 - 4 (1 bit)
access : read-only

IFCRC : CRC Controller Interrupt Status Flag (Read Only)\nThis bit indicates the interrupt status of CRC controller
bits : 16 - 16 (1 bit)
access : read-only



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