PWM0

CTRLDn : Center Re-load\nEach bit n controls the corresponding PWM0 channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
bits : 0 - 5 (6 bit)
access : read-write

IMMLDENn : Immediately Load Enable Bits\nEach bit n controls the corresponding PWM0 channel n.\nNote: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

0 : 0

PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit

1 : 1

PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT

End of enumeration elements list.

DBGHALT : ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled, PWM0 all counters will keep current value until exit ICE debug mode. \nNote:This bit is write protected. Refer toSYS_REGLCTL register.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

ICE debug mode counter halt Disabled

#1 : 1

ICE debug mode counter halt Enabled

End of enumeration elements list.

DBGTRIOFF : ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM0 pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

ICE debug mode acknowledgement effects PWM0 output

#1 : 1

ICE debug mode acknowledgement disabled

End of enumeration elements list.

PWM0_CLKSRC (CLKSRC)

PWM0 Clock Source Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECLKSRC0 : PWM0_CH01 External Clock Source Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 0

PWMx_CLK, x denotes 0 or 1

#001 : 1

TIMER0 overflow

#010 : 2

TIMER1 overflow

#011 : 3

TIMER2 overflow

#100 : 4

TIMER3 overflow

End of enumeration elements list.

ECLKSRC2 : PWM0_CH23 External Clock Source Select
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 0

PWMx_CLK, x denotes 0 or 1

#001 : 1

TIMER0 overflow

#010 : 2

TIMER1 overflow

#011 : 3

TIMER2 overflow

#100 : 4

TIMER3 overflow

End of enumeration elements list.

ECLKSRC4 : PWM0_CH45 External Clock Source Select
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#000 : 0

PWMx_CLK, x denotes 0 or 1

#001 : 1

TIMER0 overflow

#010 : 2

TIMER1 overflow

#011 : 3

TIMER2 overflow

#100 : 4

TIMER3 overflow

End of enumeration elements list.

PWM0_STATUS (STATUS)

PWM0 Status Register
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTMAX0 : Time-base Counter 0 Equal to 0xFFFF Latched Status
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

indicates the time-base counter never reached its maximum value 0xFFFF

#1 : 1

indicates the time-base counter reached its maximum value, software can write 1 to clear this bit

End of enumeration elements list.

CNTMAX2 : Time-base Counter 2 Equal to 0xFFFF Latched Status
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

indicates the time-base counter never reached its maximum value 0xFFFF

#1 : 1

indicates the time-base counter reached its maximum value, software can write 1 to clear this bit

End of enumeration elements list.

CNTMAX4 : Time-base Counter 4 Equal to 0xFFFF Latched Status
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

indicates the time-base counter never reached its maximum value 0xFFFF

#1 : 1

indicates the time-base counter reached its maximum value, software can write 1 to clear this bit

End of enumeration elements list.

ADCTRGn : ADC Start of Conversion Status\nEach bit n controls the corresponding PWM0 channel n.
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

0 : 0

Indicates no ADC start of conversion trigger event has occurred

1 : 1

Indicates an ADC start of conversion trigger event has occurred, software can write 1 to clear this bit

End of enumeration elements list.

PWM0_CLKPSC0_1 (CLKPSC0_1)

PWM0 Clock Pre-Scale Register 0_1
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKPSC : PWM0 Counter Clock Pre-scale \nThe clock of PWM0 counter is decided by clock prescaler. Each PWM0 pair share one PWM0 counter clock prescaler. The clock of PWM0 counter is divided by (CLKPSC+ 1).
bits : 0 - 11 (12 bit)
access : read-write

PWM0_CLKPSC2_3 (CLKPSC2_3)

PWM0 Clock Pre-Scale Register 2_3
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0_CLKPSC4_5 (CLKPSC4_5)

PWM0 Clock Pre-Scale Register 4_5
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0_CNTEN (CNTEN)

PWM0 Counter Enable Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTEN0 : PWM0 Counter Enable Bit 0
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0 Counter0_1 and clock prescaler0 Stop Running

#1 : 1

PWM0 Counter0_1 and clock prescaler0 Start Running

End of enumeration elements list.

CNTEN2 : PWM0 Counter Enable Bit 2
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0 Counter2_3 and clock prescaler2 Stop Running

#1 : 1

PWM0 Counter2_3 and clock prescaler2 Start Running

End of enumeration elements list.

CNTEN4 : PWM0 Counter Enable Bit4
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0 Counter4_5 and clock prescaler4 Stop Running. ....

#1 : 1

PWM0 Counter4_5 and clock prescaler4 Start Running

End of enumeration elements list.

PWM0_CAPINEN (CAPINEN)

PWM0 Capture Input Enable Register
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAPINENn : Capture Input Enable Bits\nEach bit n controls the corresponding PWM0 channel n.
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : 0

PWM0 Channel capture input path Disabled. The input of PWM0 channel capture function is always regarded as 0

1 : 1

PWM0 Channel capture input path Enabled. The input of PWM0 channel capture function comes from correlative multifunction pin

End of enumeration elements list.

PWM0_CAPCTL (CAPCTL)

PWM0 Capture Control Register
address_offset : 0x204 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAPENn : Capture Function Enable Bits\nEach bit n controls the corresponding PWM0 channel n.
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : 0

Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated

1 : 1

Capture function Enabled. Capture latched the PWM0 counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)

End of enumeration elements list.

CAPINVn : Capture Inverter Enable Bits\nEach bit n controls the corresponding PWM0 channel n.
bits : 8 - 13 (6 bit)
access : read-write

Enumeration:

0 : 0

Capture source inverter Disabled

1 : 1

Capture source inverter Enabled. Reverse the input signal from GPIO

End of enumeration elements list.

RCRLDENn : Rising Capture Reload Enable Bits\nEach bit n controls the corresponding PWM0 channel n.
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

0 : 0

Risingcapture reload counter Disabled

1 : 1

Risingcapture reload counter Enabled

End of enumeration elements list.

FCRLDENn : Falling Capture Reload EnableBits\nEach bit n controls the corresponding PWM0 channel n.
bits : 24 - 29 (6 bit)
access : read-write

Enumeration:

0 : 0

Falling capture reload counter Disabled

1 : 1

Falling capture reload counter Enabled

End of enumeration elements list.

PWM0_CAPSTS (CAPSTS)

PWM0 Capture Status Register
address_offset : 0x208 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CRIFOVn : Capture Rising Interrupt Flag Overrun Status(Read Only)\nThis flag indicatesif rising latch happenedwhen the corresponding CAPRIFis 1. Each bit n controls the corresponding PWM0 channel n.\nNote:This bit will be cleared automatically when user clear corresponding CAPRIF.
bits : 0 - 5 (6 bit)
access : read-only

CFIFOVn : Capture Falling Interrupt Flag Overrun Status(Read Only)\nThis flag indicatesif falling latch happenedwhen the corresponding CAPFIFis 1. Each bit n controls the corresponding PWM0 channel n.\nNote:This bit will be cleared automatically when user clear corresponding CAPFIF.
bits : 8 - 13 (6 bit)
access : read-only

PWM0_RCAPDAT0 (RCAPDAT0)

PWM0 Rising Capture Data Register 0
address_offset : 0x20C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RCAPDAT : PWM0 Rising Capture Data Register(Read Only)\nWhen rising capture condition happened, the PWM0 counter value will be saved in this register.
bits : 0 - 15 (16 bit)
access : read-only

PWM0_FCAPDAT0 (FCAPDAT0)

PWM0 Falling Capture Data Register 0
address_offset : 0x210 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FCAPDAT : PWM0 Falling Capture Data Register(Read Only)\nWhen falling capture condition happened, the PWM0 counter value will be saved in this register.
bits : 0 - 15 (16 bit)
access : read-only

PWM0_RCAPDAT1 (RCAPDAT1)

PWM0 Rising Capture Data Register 1
address_offset : 0x214 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0_FCAPDAT1 (FCAPDAT1)

PWM0 Falling Capture Data Register 1
address_offset : 0x218 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0_RCAPDAT2 (RCAPDAT2)

PWM0 Rising Capture Data Register 2
address_offset : 0x21C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0_FCAPDAT2 (FCAPDAT2)

PWM0 Falling Capture Data Register 2
address_offset : 0x220 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0_RCAPDAT3 (RCAPDAT3)

PWM0 Rising Capture Data Register 3
address_offset : 0x224 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0_FCAPDAT3 (FCAPDAT3)

PWM0 Falling Capture Data Register 3
address_offset : 0x228 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0_RCAPDAT4 (RCAPDAT4)

PWM0 Rising Capture Data Register 4
address_offset : 0x22C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0_FCAPDAT4 (FCAPDAT4)

PWM0 Falling Capture Data Register 4
address_offset : 0x230 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0_RCAPDAT5 (RCAPDAT5)

PWM0 Rising Capture Data Register 5
address_offset : 0x234 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0_FCAPDAT5 (FCAPDAT5)

PWM0 Falling Capture Data Register 5
address_offset : 0x238 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0_CNTCLR (CNTCLR)

PWM0 Clear Counter Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTCLR0 : Clear PWM0 Counter Control Bit 0\nIt is automatically cleared by hardware.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Clear 16-bit PWM0 counter to 0000H

End of enumeration elements list.

CNTCLR2 : Clear PWM0 Counter Control Bit 2\nIt is automatically cleared by hardware.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Clear 16-bit PWM0 counter to 0000H

End of enumeration elements list.

CNTCLR4 : Clear PWM0 Counter Control Bit 4\nIt is automatically cleared by hardware.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Clear 16-bit PWM0 counter to 0000H

End of enumeration elements list.

PWM0_CAPIEN (CAPIEN)

PWM0 Capture Interrupt Enable Register
address_offset : 0x250 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAPRIENn : PWM0 Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM0 channel n.
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : 0

Capture rising edge latch interrupt Disabled

1 : 1

Capture rising edge latch interrupt Enabled

End of enumeration elements list.

CAPFIENn : PWM0 Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM0 channel n.
bits : 8 - 13 (6 bit)
access : read-write

Enumeration:

0 : 0

Capture falling edge latch interrupt Disabled

1 : 1

Capture falling edge latch interrupt Enabled

End of enumeration elements list.

PWM0_CAPIF (CAPIF)

PWM0 Capture Interrupt Flag Register
address_offset : 0x254 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAPRIFn : PWM0 Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM0 channel n.
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : 0

No capture rising latch condition happened

1 : 1

Capture rising latch condition happened, this flag will be set to high

End of enumeration elements list.

CAPFIFn : PWM0 Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM0 channel n.
bits : 8 - 13 (6 bit)
access : read-write

Enumeration:

0 : 0

No capture falling latch condition happened

1 : 1

Capture falling latch condition happened, this flag will be set to high

End of enumeration elements list.

PWM0_PERIOD0 (PERIOD0)

PWM0 Period Register 0
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PERIOD : PWM0 Period Register\nUp-Count mode: In this mode, PWM0 counter counts from 0 to PERIOD, and restarts from 0.\nDown-Count mode: In this mode, PWM0 counter counts from PERIOD to 0, and restarts from PERIOD.
bits : 0 - 15 (16 bit)
access : read-write

PWM0_SELFTEST (SELFTEST)

PWM0 Self-test Mode Enable
address_offset : 0x300 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0_PBUF0 (PBUF0)

PWM0 PERIOD0 Buffer
address_offset : 0x304 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PBUF : PWM0 Period Register Buffer(Read Only)\nUsed as PERIOD active register.
bits : 0 - 15 (16 bit)
access : read-only

PWM0_PBUF2 (PBUF2)

PWM0 PERIOD2 Buffer
address_offset : 0x30C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0_PBUF4 (PBUF4)

PWM0 PERIOD4 Buffer
address_offset : 0x314 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0_CMPBUF0 (CMPBUF0)

PWM0 CMPDAT0 Buffer
address_offset : 0x31C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CMPBUF : PWM0 Comparator Register Buffer(Read Only)\nUsed as CMP active register.
bits : 0 - 15 (16 bit)
access : read-only

PWM0_CMPBUF1 (CMPBUF1)

PWM0 CMPDAT1 Buffer
address_offset : 0x320 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0_CMPBUF2 (CMPBUF2)

PWM0 CMPDAT2 Buffer
address_offset : 0x324 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0_CMPBUF3 (CMPBUF3)

PWM0 CMPDAT3 Buffer
address_offset : 0x328 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0_CMPBUF4 (CMPBUF4)

PWM0 CMPDAT4 Buffer
address_offset : 0x32C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0_CMPBUF5 (CMPBUF5)

PWM0 CMPDAT5 Buffer
address_offset : 0x330 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0_PERIOD2 (PERIOD2)

PWM0 Period Register 2
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0_CTL1 (CTL1)

PWM0 Control Register 1
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTTYPE0 : PWM0 Counter Behavior Type 0\nEach bit n controls corresponding PWM0 channel n.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

Up counter type (supports in capture mode)

#01 : 1

Down count type (supports in capture mode)

#10 : 2

Up-down counter type

#11 : 3

Reserved

End of enumeration elements list.

CNTTYPE2 : PWM0 Counter Behavior Type 2\nEach bit n controls corresponding PWM0 channel n.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 0

Up counter type (supports in capture mode)

#01 : 1

Down count type (supports in capture mode)

#10 : 2

Up-down counter type

#11 : 3

Reserved

End of enumeration elements list.

CNTTYPE4 : PWM0 Counter Behavior Type 4\nEach bit n controls corresponding PWM0 channel n.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#00 : 0

Up counter type (supports in capture mode)

#01 : 1

Down count type (supports in capture mode)

#10 : 2

Up-down counter type

#11 : 3

Reserved

End of enumeration elements list.

PWMMODEn : PWM0 Mode\nEach bit n controls the corresponding PWM0 channel n.\nNote: When operating in group function, these bits must all set to the same mode.
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : 0

PWM0 independent mode

1 : 1

PWM0 complementary mode

End of enumeration elements list.

PWM0_PERIOD4 (PERIOD4)

PWM0 Period Register 4
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0_CMPDAT0 (CMPDAT0)

PWM0 Comparator Register 0
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPDAT : PWM0 Comparator Register\nCMPDAT use to compare with CNTR to generate PWM0 waveform, interrupt and trigger ADC.\nIn independent mode, CMPDAT0~5 denote as 6 independent PWM0_CH0~5 compared point.\nIn complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs PWM0_CH0 and PWM0_CH1, PWM0_CH2 and PWM0_CH3, PWM0_CH4 and PWM0_CH5.
bits : 0 - 15 (16 bit)
access : read-write

PWM0_CMPDAT1 (CMPDAT1)

PWM0 Comparator Register 1
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0_CMPDAT2 (CMPDAT2)

PWM0 Comparator Register 2
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0_CMPDAT3 (CMPDAT3)

PWM0 Comparator Register 3
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0_CMPDAT4 (CMPDAT4)

PWM0 Comparator Register 4
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0_CMPDAT5 (CMPDAT5)

PWM0 Comparator Register 5
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0_DTCTL0_1 (DTCTL0_1)

PWM0 Dead-Time Control Register 0_1
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTCNT : Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote:This register is write protected. Refer toSYS_REGLCTL register.
bits : 0 - 11 (12 bit)
access : read-write

DTEN : Enable Dead-time Insertion for PWM0 Pair (PWM0_CH0, PWM0_CH1)(PWM0_CH2, PWM0_CH3)(PWM0_CH4, PWM0_CH5)(Write Protect)\nDead-time insertion is only active when this PWM0 pair complementary mode is enabled. If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.\nNote:This register is write protected. Refer toSYS_REGLCTL register.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Dead-time insertion Disabled on the pin pair

#1 : 1

Dead-time insertion Enabled on the pin pair

End of enumeration elements list.

DTCKSEL : Dead-time Clock Select (Write Protect)\nNote:This register is write protected. Refer toREGWRPROT register.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Dead-time clock source from PWM0_CLKn

#1 : 1

Dead-time clock source from prescaler output

End of enumeration elements list.

PWM0_DTCTL2_3 (DTCTL2_3)

PWM0 Dead-Time Control Register 2_3
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0_DTCTL4_5 (DTCTL4_5)

PWM0 Dead-Time Control Register 4_5
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0_CNT0 (CNT0)

PWM0 Counter Register 0
address_offset : 0x90 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CNT : PWM0 Data Register(Read Only)\nUser can monitor CNTR to know the current value in 16-bit period counter.
bits : 0 - 15 (16 bit)
access : read-only

DIRF : PWM0 Direction Indicator Flag (Read Only)
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

#0 : 0

Counter is Down count

#1 : 1

Counter is UP count

End of enumeration elements list.

PWM0_CNT2 (CNT2)

PWM0 Counter Register 2
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0_CNT4 (CNT4)

PWM0 Counter Register 4
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0_WGCTL0 (WGCTL0)

PWM0Waveform Generation Control Register 0
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ZPCTLn : PWM0 Zero Point Control\nEach bit n controls the corresponding PWM0 channel n.\nPWM0 can control output level when PWM0 counter count to zero.
bits : 0 - 11 (12 bit)
access : read-write

Enumeration:

00 : 0

Do nothing

01 : 1

PWM0 zero point output Low

10 : 10

PWM0 zero point output High

11 : 11

PWM0 zero point output Toggle

End of enumeration elements list.

PRDPCTLn : PWM0 Period (Center) Point Control\nEach bit n controls the corresponding PWM0 channel n.\nPWM0 can control output level when PWM0 counter count to (PERIODn+1).\nNote: This bit is center point control when PWM0 counter operating in up-down counter type.
bits : 16 - 27 (12 bit)
access : read-write

Enumeration:

00 : 0

Do nothing

01 : 1

PWM0 period (center) point output Low

10 : 10

PWM0 period (center) point output High

11 : 11

PWM0 period (center) point output Toggle

End of enumeration elements list.

PWM0_WGCTL1 (WGCTL1)

PWM0Waveform Generation Control Register 1
address_offset : 0xB4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPUCTLn : PWM0 Compare Up Point Control\nEach bit n controls the corresponding PWM0 channel n.\nPWM0 can control output level when PWM0 counter up count to CMPDAT.\nNote: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
bits : 0 - 11 (12 bit)
access : read-write

Enumeration:

00 : 0

Do nothing

01 : 1

PWM0 compare up point output Low

10 : 10

PWM0 compare up point output High

11 : 11

PWM0 compare up point output Toggle

End of enumeration elements list.

CMPDCTLn : PWM0 Compare Down Point Control\nEach bit n controls the corresponding PWM0 channel n.\nPWM0 can control output level when PWM0 counter down count to CMPDAT.\nNote: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
bits : 16 - 27 (12 bit)
access : read-write

Enumeration:

00 : 0

Do nothing

01 : 1

PWM0 compare down point output Low

10 : 10

PWM0 compare down point output High

11 : 11

PWM0 compare down point output Toggle

End of enumeration elements list.

PWM0_MSKEN (MSKEN)

PWM0 Mask Enable Register
address_offset : 0xB8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSKENn : PWM0 Mask Enable Bits\nEach bit n controls the corresponding PWM0 channel n.\nThe PWM0 output signal will be masked when this bit is enabled. The corresponding PWM0 channel n will output MSKDATn (PWM0_MSK[5:0]) data.
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : 0

PWM0 output signal is non-masked

1 : 1

PWM0 output signal is masked and output MSKDATn data

End of enumeration elements list.

PWM0_MSK (MSK)

PWM0 Mask Data Register
address_offset : 0xBC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSKDATn : PWM0 Mask Data Bits\nThis data bit control the state of PWM0_CHn output pin, if corresponding mask function is enabled.
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : 0

Output logic low to PWM0_CHn

1 : 1

Output logic high to PWM0_CHn

End of enumeration elements list.

PWM0_BNF (BNF)

PWM0 Brake Noise Filter Register
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRK0FEN : PWM0 Brake 0 Noise Filter Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Noise filter of PWM0 Brake 0 Disabled

#1 : 1

Noise filter of PWM0 Brake 0 Enabled

End of enumeration elements list.

BRK0FCS : Brake 0 Edge Detector Filter Clock Selection
bits : 1 - 3 (3 bit)
access : read-write

Enumeration:

#000 : 0

Filter clock = HCLK

#001 : 1

Filter clock = HCLK/2

#010 : 2

Filter clock = HCLK/4

#011 : 3

Filter clock = HCLK/8

#100 : 4

Filter clock = HCLK/16

#101 : 5

Filter clock = HCLK/32

#110 : 6

Filter clock = HCLK/64

#111 : 7

Filter clock = HCLK/128

End of enumeration elements list.

BRK0FCNT : Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK1FCNT.
bits : 4 - 6 (3 bit)
access : read-write

BRK0PINV : Brake 0 Pin Inverse
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

The state of pin PWMx_BRAKE0 is passed to the negative edge detector

#1 : 1

The inversed state of pin PWMx_BRAKE10 is passed to the negative edge detector

End of enumeration elements list.

BRK1FEN : PWM0 Brake 1 Noise Filter Enable Bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Noise filter of PWM0 Brake 1 Disabled

#1 : 1

Noise filter of PWM0 Brake 1 Enabled

End of enumeration elements list.

BRK1FCS : Brake 1 Edge Detector Filter Clock Selection
bits : 9 - 11 (3 bit)
access : read-write

Enumeration:

#000 : 0

Filter clock = HCLK

#001 : 1

Filter clock = HCLK/2

#010 : 2

Filter clock = HCLK/4

#011 : 3

Filter clock = HCLK/8

#100 : 4

Filter clock = HCLK/16

#101 : 5

Filter clock = HCLK/32

#110 : 6

Filter clock = HCLK/64

#111 : 7

Filter clock = HCLK/128

End of enumeration elements list.

BRK1FCNT : Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT.
bits : 12 - 14 (3 bit)
access : read-write

BRK1PINV : Brake 1 Pin Inverse
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

The state of pin PWMx_BRAKE1 is passed to the negative edge detector

#1 : 1

The inversed state of pin PWMx_BRAKE1 is passed to the negative edge detector

End of enumeration elements list.

BK0SRC : Brake 0 Pin Source Select\nFor PWM0 setting:
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Brake 0 pin source come from PWM0_BRAKE0.\nBrake 0 pin source come from PWM1_BRAKE0

#1 : 1

Brake 0 pin source come from PWM1_BRAKE0.\nBrake 0 pin source come from PWM0_BRAKE0

End of enumeration elements list.

BK1SRC : Brake 1 Pin Source Select\nFor PWM0 setting:
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Brake 1 pin source come from PWM0_BRAKE1.\nBrake 1 pin source come from PWM1_BRAKE1

#1 : 1

Brake 1 pin source come from PWM1_BRAKE1.\nBrake 1 pin source come from PWM0_BRAKE1

End of enumeration elements list.

PWM0_FAILBRK (FAILBRK)

PWM0 System Fail Brake Control Register
address_offset : 0xC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BODBRKEN : Brown-out Detection Trigger PWM0 Brake Function 0 Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Brake Function triggered by BOD Disabled

#1 : 1

Brake Function triggered by BOD Enabled

End of enumeration elements list.

CORBRKEN : Core Lockup Detection Trigger PWM0 Brake Function 0 Enable Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Brake Function triggered by Core lockup detection Disabled

#1 : 1

Brake Function triggered by Core lockup detection Enabled

End of enumeration elements list.

PWM0_BRKCTL0_1 (BRKCTL0_1)

PWM0 Brake Edge Detect Control Register 0_1
address_offset : 0xC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRKP0EEN : Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

BKP0 pin as edge-detect brake source Disabled

#1 : 1

BKP0 pin as edge-detect brake source Enabled

End of enumeration elements list.

BRKP1EEN : Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

BKP1 pin as edge-detect brake source Disabled

#1 : 1

BKP1 pin as edge-detect brake source Enabled

End of enumeration elements list.

SYSEEN : Enable System Fail As Edge-detect Brake Source(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

System Fail condition as edge-detect brake source Disabled

#1 : 1

System Fail condition as edge-detect brake source Enabled

End of enumeration elements list.

BRKP0LEN : Enable BKP0 Pin As Level-detect Brake Source(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWMx_BRAKE0 pin as level-detect brake source Disabled

#1 : 1

PWMx_BRAKE0 pin as level-detect brake source Enabled

End of enumeration elements list.

BRKP1LEN : Enable BKP1 Pin As Level-detect Brake Source(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWMx_BRAKE1 pin as level-detect brake source Disabled

#1 : 1

PWMx_BRAKE1 pin as level-detect brake source Enabled

End of enumeration elements list.

SYSLEN : Enable System Fail As Level-detect Brake Source(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

System Fail condition as level-detect brake source Disabled

#1 : 1

System Fail condition as level-detect brake source Enabled

End of enumeration elements list.

BRKAEVEN : PWM0 Brake Action Select for Even Channel (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register.
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#00 : 0

PWM0 even channelbrake function not affect channel output

#01 : 1

PWM0 even channel output tri-state when brake happened

#10 : 2

PWM0 even channel output low level whenbrake happened

#11 : 3

PWM0 even channel output high level when brake happened

End of enumeration elements list.

BRKAODD : PWM0 Brake Action Select for Odd Channel (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register.
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

#00 : 0

PWM0 odd channel brake function not affect channel output

#01 : 1

PWM0 odd channel output tri-state when brake happened

#10 : 2

PWM0 odd channel output low level whenbrake happened

#11 : 3

PWM0 odd channel output high level when brake happened

End of enumeration elements list.

PWM0_BRKCTL2_3 (BRKCTL2_3)

PWM0 Brake Edge Detect Control Register 2_3
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0_BRKCTL4_5 (BRKCTL4_5)

PWM0 Brake Edge Detect Control Register 4_5
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0_POLCTL (POLCTL)

PWM0 Pin Polar Inverse Register
address_offset : 0xD4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINVn : PWM0 PIN Polar Inverse Control\nThe register controls polarity state of PWM0 output. Each bit n controls the corresponding PWM0 channel n.
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : 0

PWM0 output polar inverse Disabled

1 : 1

PWM0 output polar inverse Enabled

End of enumeration elements list.

PWM0_POEN (POEN)

PWM0 Output Enable Register
address_offset : 0xD8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POENn : PWM0 Pin Output Enable Bits\nEach bit n controls the corresponding PWM0 channel n.
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : 0

PWM0 pin at tri-state

1 : 1

PWM0 pin in output mode

End of enumeration elements list.

PWM0_SWBRK (SWBRK)

PWM0 Software Brake Control Register
address_offset : 0xDC Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

BRKETRGn : PWM0 Edge Brake Software Trigger (Write Only)(Write Protect)\nEach bit n controls the corresponding PWM0 pair n.\nWrite 1 to this bit will trigger Edge brake, and set BRKEIFn to 1 in PWM0_INTSTS1 register. \nNote:This register is write protected. Refer toSYS_REGLCTL register.
bits : 0 - 2 (3 bit)
access : write-only

BRKLTRGn : PWM0 Level Brake Software Trigger (Write Only)(Write Protect)\nEach bit n controls the corresponding PWM0 pair n.\nWrite 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM0_INTSTS1 register. \nNote:This register is write protected. Refer toSYS_REGLCTL register.
bits : 8 - 10 (3 bit)
access : write-only

PWM0_INTEN0 (INTEN0)

PWM0 Interrupt Enable Register 0
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ZIEN0 : PWM0 Zero Point Interrupt Enable Bit 0\nNote: Odd channels will read always 0 at complementary mode.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0counter0_1 zero point interrupt Disabled

#1 : 1

PWM0counter0_1 zero point interrupt Enabled

End of enumeration elements list.

ZIEN2 : PWM0 Zero Point Interrupt Enable Bit 2\nNote: Odd channels will read always 0 at complementary mode.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0counter2_3 zero point interrupt Disabled

#1 : 1

PWM0counter2_3 zero point interrupt Enabled

End of enumeration elements list.

ZIEN4 : PWM0 Zero Point Interrupt Enable Bit 4\nNote: Odd channels will read always 0 at complementary mode.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0counter4_5 zero point interrupt Disabled

#1 : 1

PWM0counter4_5 zero point interrupt Enabled

End of enumeration elements list.

PIEN0 : PWM0 Period Point Interrupt Enable Bit 0\nNote: When operating in up-down counter type, period point means center point.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0counter0_1 period point interrupt Disabled

#1 : 1

PWM0counter0_1 period point interrupt Enabled

End of enumeration elements list.

PIEN2 : PWM0 Period Point Interrupt Enable Bit 2\nNote: When operating in up-down counter type, period point means center point.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0counter2_3 period point interrupt Disabled

#1 : 1

PWM0counter2_3 period point interrupt Enabled

End of enumeration elements list.

PIEN4 : PWM0 Period Point Interrupt Enable Bit 4\nNote: When operating in up-down counter type, period point means center point.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0counter4_5 period point interrupt Disabled

#1 : 1

PWM0counter4_5 period point interrupt Enabled

End of enumeration elements list.

CMPUIENn : PWM0 Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM0 channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

0 : 0

Compare up count interrupt Disabled

1 : 1

Compare up count interrupt Enabled

End of enumeration elements list.

CMPDIENn : PWM0 Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM0 channel n.\nNote: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
bits : 24 - 29 (6 bit)
access : read-write

Enumeration:

0 : 0

Compare down count interrupt Disabled

1 : 1

Compare down count interrupt Enabled

End of enumeration elements list.

PWM0_INTEN1 (INTEN1)

PWM0 Interrupt Enable Register 1
address_offset : 0xE4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRKEIEN0_1 : PWM0 Edge-detect Brake Interrupt Enable Bitfor Channel0/1(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge-detect Brake interrupt for channel0/1 Disabled

#1 : 1

Edge-detect Brake interrupt for channel0/1 Enabled

End of enumeration elements list.

BRKEIEN2_3 : PWM0 Edge-detect Brake Interrupt Enable Bitfor Channel2/3(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge-detect Brake interrupt for channel2/3 Disabled

#1 : 1

Edge-detect Brake interrupt for channel2/3 Enabled

End of enumeration elements list.

BRKEIEN4_5 : PWM0 Edge-detect Brake Interrupt Enable Bitfor Channel4/5(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge-detect Brake interrupt for channel4/5 Disabled

#1 : 1

Edge-detect Brake interrupt for channel4/5 Enabled

End of enumeration elements list.

BRKLIEN0_1 : PWM0 Level-detect Brake Interrupt Enable Bitfor Channel0/1(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Level-detect Brake interrupt for channel0/1 Disabled

#1 : 1

Level-detect Brake interrupt for channel0/1 Enabled

End of enumeration elements list.

BRKLIEN2_3 : PWM0 Level-detect Brake Interrupt Enable Bitfor Channel2/3(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Level-detect Brake interrupt for channel2/3 Disabled

#1 : 1

Level-detect Brake interrupt for channel2/3 Enabled

End of enumeration elements list.

BRKLIEN4_5 : PWM0 Level-detect Brake Interrupt Enable Bit for Channel4/5(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Level-detect Brake interrupt for channel4/5 Disabled

#1 : 1

Level-detect Brake interrupt for channel4/5 Enabled

End of enumeration elements list.

PWM0_INTSTS0 (INTSTS0)

PWM0 Interrupt Flag Register 0
address_offset : 0xE8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ZIF0 : PWM0 Zero Point Interrupt Flag 0\nThis bit is set by hardware when PWM0_CH0 counter reaches zero, software can write 1 to clear this bit to zero.
bits : 0 - 0 (1 bit)
access : read-write

ZIF2 : PWM0 Zero Point Interrupt Flag 2\nThis bit is set by hardware when PWM0_CH2 counter reaches zero, software can write 1 to clear this bit to zero.
bits : 2 - 2 (1 bit)
access : read-write

ZIF4 : PWM0 Zero Point Interrupt Flag 4\nThis bit is set by hardware when PWM0_CH4 counter reaches zero, software can write 1 to clear this bit to zero.
bits : 4 - 4 (1 bit)
access : read-write

PIF0 : PWM0 Period Point Interrupt Flag 0\nThis bit is set by hardware when PWM0_CH0 counter reaches PWM0_PERIOD0, software can write 1 to clear this bit to zero.
bits : 8 - 8 (1 bit)
access : read-write

PIF2 : PWM0 Period Point Interrupt Flag 2\nThis bit is set by hardware when PWM0_CH2 counter reaches PWM0_PERIOD2, software can write 1 to clear this bit to zero.
bits : 10 - 10 (1 bit)
access : read-write

PIF4 : PWM0 Period Point Interrupt Flag 4\nThis bit is set by hardware when PWM0_CH4 counter reaches PWM0_PERIOD4, software can write 1 to clear this bit to zero.
bits : 12 - 12 (1 bit)
access : read-write

CMPUIFn : PWM0 Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM0 counter up count and reaches PWM0_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM0 channel n.\nNote1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.\nNote2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
bits : 16 - 21 (6 bit)
access : read-write

CMPDIFn : PWM0 Compare Down Count Interrupt Flag\nEach bit n controls the corresponding PWM0 channel n.\nFlag is set by hardware when PWM0 counter down count and reaches PWM0_CMPDATn, software can clear this bit by writing 1 to it.\nNote1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.\nNote2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
bits : 24 - 29 (6 bit)
access : read-write

PWM0_INTSTS1 (INTSTS1)

PWM0 Interrupt Flag Register 1
address_offset : 0xEC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRKEIF0 : PWM0 Channel0 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0 channel0 edge-detect brake event do not happened

#1 : 1

When PWM0 channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear

End of enumeration elements list.

BRKEIF1 : PWM0 Channel1 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0 channel1 edge-detect brake event do not happened

#1 : 1

When PWM0 channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear

End of enumeration elements list.

BRKEIF2 : PWM0 Channel2 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0 channel2 edge-detect brake event do not happened

#1 : 1

When PWM0 channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear

End of enumeration elements list.

BRKEIF3 : PWM0 Channel3 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0 channel3 edge-detect brake event do not happened

#1 : 1

When PWM0 channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear

End of enumeration elements list.

BRKEIF4 : PWM0 Channel4 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0 channel4 edge-detect brake event do not happened

#1 : 1

When PWM0 channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear

End of enumeration elements list.

BRKEIF5 : PWM0 Channel5 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0 channel5 edge-detect brake event do not happened

#1 : 1

When PWM0 channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear

End of enumeration elements list.

BRKLIF0 : PWM0 Channel0 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0 channel0 level-detect brake event do not happened

#1 : 1

When PWM0 channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear

End of enumeration elements list.

BRKLIF1 : PWM0 Channel1 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0 channel1 level-detect brake event do not happened

#1 : 1

When PWM0 channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear

End of enumeration elements list.

BRKLIF2 : PWM0 Channel2 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0 channel2 level-detect brake event do not happened

#1 : 1

When PWM0 channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear

End of enumeration elements list.

BRKLIF3 : PWM0 Channel3 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0 channel3 level-detect brake event do not happened

#1 : 1

When PWM0 channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear

End of enumeration elements list.

BRKLIF4 : PWM0 Channel4 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0 channel4 level-detect brake event do not happened

#1 : 1

When PWM0 channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear

End of enumeration elements list.

BRKLIF5 : PWM0 Channel5 Level-detect Brake Interrupt Flag(Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0 channel5 level-detect brake event do not happened

#1 : 1

When PWM0 channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear

End of enumeration elements list.

BRKESTS0 : PWM0 Channel0 Edge-detect Brake Status (Read Only)
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

#0 : 0

PWM0 channel0 edge-detect brake state is released

#1 : 1

When PWM0 channel0 edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM0 channel0 at brake state, writing 1 to clear

End of enumeration elements list.

BRKESTS1 : PWM0 Channel1 Edge-detect Brake Status (Read Only)
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

#0 : 0

PWM0 channel1 edge-detect brake state is released

#1 : 1

When PWM0 channel1 edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM0 channel1 at brake state, writing 1 to clear

End of enumeration elements list.

BRKESTS2 : PWM0 Channel2 Edge-detect Brake Status (Read Only)
bits : 18 - 18 (1 bit)
access : read-only

Enumeration:

#0 : 0

PWM0 channel2 edge-detect brake state is released

#1 : 1

When PWM0 channel2 edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM0 channel2 at brake state, writing 1 to clear

End of enumeration elements list.

BRKESTS3 : PWM0 Channel3 Edge-detect Brake Status (Read Only)
bits : 19 - 19 (1 bit)
access : read-only

Enumeration:

#0 : 0

PWM0 channel3 edge-detect brake state is released

#1 : 1

When PWM0 channel3 edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM0 channel3 at brake state, writing 1 to clear

End of enumeration elements list.

BRKESTS4 : PWM0 Channel4 Edge-detect Brake Status (Read Only)
bits : 20 - 20 (1 bit)
access : read-only

Enumeration:

#0 : 0

PWM0 channel4 edge-detect brake state is released

#1 : 1

When PWM0 channel4 edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM0 channel4 at brake state, writing 1 to clear

End of enumeration elements list.

BRKESTS5 : PWM0 Channel5 Edge-detect Brake Status (Read Only)
bits : 21 - 21 (1 bit)
access : read-only

Enumeration:

#0 : 0

PWM0 channel5 edge-detect brake state is released

#1 : 1

When PWM0 channel5 edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM0 channel5 at brake state, writing 1 to clear

End of enumeration elements list.

BRKLSTS0 : PWM0 Channel0 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM0 will release brake state until current PWM0 period finished. The PWM0 waveform will start output from next full PWM0 period.
bits : 24 - 24 (1 bit)
access : read-only

Enumeration:

#0 : 0

PWM0 channel0 level-detect brake state is released

#1 : 1

When PWM0 channel0 level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM0 channel0 at brake state

End of enumeration elements list.

BRKLSTS1 : PWM0 Channel1 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM0 will release brake state until current PWM0 period finished. The PWM0 waveform will start output from next full PWM0 period.
bits : 25 - 25 (1 bit)
access : read-only

Enumeration:

#0 : 0

PWM0 channel1 level-detect brake state is released

#1 : 1

When PWM0 channel1 level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM0 channel1 at brake state

End of enumeration elements list.

BRKLSTS2 : PWM0 Channel2 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM0 will release brake state until current PWM0 period finished. The PWM0 waveform will start output from next full PWM0 period.
bits : 26 - 26 (1 bit)
access : read-only

Enumeration:

#0 : 0

PWM0 channel2 level-detect brake state is released

#1 : 1

When PWM0 channel2 level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM0 channel2 at brake state

End of enumeration elements list.

BRKLSTS3 : PWM0 Channel3 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM0 will release brake state until current PWM0 period finished. The PWM0 waveform will start output from next full PWM0 period.
bits : 27 - 27 (1 bit)
access : read-only

Enumeration:

#0 : 0

PWM0 channel3 level-detect brake state is released

#1 : 1

When PWM0 channel3 level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM0 channel3 at brake state

End of enumeration elements list.

BRKLSTS4 : PWM0 Channel4 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM0 will release brake state until current PWM0 period finished. The PWM0 waveform will start output from next full PWM0 period.
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#0 : 0

PWM0 channel4 level-detect brake state is released

#1 : 1

When PWM0 channel4 level-detect brake detects a falling edgeof any enabled brake source this flag will be set to indicate the PWM0 channel4 at brake state

End of enumeration elements list.

BRKLSTS5 : PWM0 Channel5 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM0 will release brake state until current PWM0 period finished. The PWM0 waveform will start output from next full PWM0 period.
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

#0 : 0

PWM0 channel5 level-detect brake state is released

#1 : 1

When PWM0 channel5 level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM0 channel5 at brake state

End of enumeration elements list.

PWM0_ADCTS0 (ADCTS0)

PWM0 Trigger ADC Source Select Register 0
address_offset : 0xF8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGSEL0 : PWM0_CH0 Trigger ADC Source Select\nOthers reserved
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0000 : 0

PWM0_CH0 zero point

#0001 : 1

PWM0_CH0 period point

#0010 : 2

PWM0_CH0 zero or period point

#0011 : 3

PWM0_CH0 up-count CMPDAT point

#0100 : 4

PWM0_CH0 down-count CMPDAT point

#0101 : 5

Reserved

#0110 : 6

Reserved

#0111 : 7

Reserved

#1000 : 8

PWM0_CH1 up-count CMPDAT point

#1001 : 9

PWM0_CH1 down-count CMPDAT point

End of enumeration elements list.

TRGEN0 : PWM0_CH0 Trigger EADC Enable Bit
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0_CH0 Trigger EADC Disabled

#1 : 1

PWM0_CH0 Trigger EADC Enabled

End of enumeration elements list.

TRGSEL1 : PWM0_CH1 Trigger ADC Source Select\nOthers reserved
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

#0000 : 0

PWM0_CH0 zero point

#0001 : 1

PWM0_CH0 period point

#0010 : 2

PWM0_CH0 zero or period point

#0011 : 3

PWM0_CH0 up-count CMPDAT point

#0100 : 4

PWM0_CH0 down-count CMPDAT point

#0101 : 5

Reserved

#0110 : 6

Reserved

#0111 : 7

Reserved

#1000 : 8

PWM0_CH1 up-count CMPDAT point

#1001 : 9

PWM0_CH1 down-count CMPDAT point

End of enumeration elements list.

TRGEN1 : PWM0_CH1 Trigger EADC Enable Bit
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0_CH1 Trigger EADC Disabled

#1 : 1

PWM0_CH1 Trigger EADC Enabled

End of enumeration elements list.

TRGSEL2 : PWM0_CH2 Trigger ADC Source Select\nOthers reserved
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0

PWM0_CH2 zero point

#0001 : 1

PWM0_CH2 period point

#0010 : 2

PWM0_CH2 zero or period point

#0011 : 3

PWM0_CH2 up-count CMPDAT point

#0100 : 4

PWM0_CH2 down-count CMPDAT point

#0101 : 5

Reserved

#0110 : 6

Reserved

#0111 : 7

Reserved

#1000 : 8

PWM0_CH3 up-count CMPDAT point

#1001 : 9

PWM0_CH3 down-count CMPDAT point

End of enumeration elements list.

TRGEN2 : PWM0_CH2 Trigger EADC Enable Bit
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0_CH2 Trigger EADC Disabled

#1 : 1

PWM0_CH2 Trigger EADC Enabled

End of enumeration elements list.

TRGSEL3 : PWM0_CH3 Trigger ADC Source Select\nOthers reserved
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

#0000 : 0

PWM0_CH2 zero point

#0001 : 1

PWM0_CH2 period point

#0010 : 2

PWM0_CH2 zero or period point

#0011 : 3

PWM0_CH2 up-count CMPDAT point

#0100 : 4

PWM0_CH2 down-count CMPDAT point

#0101 : 5

Reserved

#0110 : 6

Reserved

#0111 : 7

Reserved

#1000 : 8

PWM0_CH3 up-count CMPDAT point

#1001 : 9

PWM0_CH3 down-count CMPDAT point

End of enumeration elements list.

TRGEN3 : PWM0_CH3 Trigger EADC Enable Bit
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0_CH3 Trigger EADC Disabled

#1 : 1

PWM0_CH3 Trigger EADC Enabled

End of enumeration elements list.

PWM0_ADCTS1 (ADCTS1)

PWM0 Trigger ADC Source Select Register 1
address_offset : 0xFC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGSEL4 : PWM0_CH4 Trigger ADC Source Select\nOthers reserved
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0000 : 0

PWM0_CH4 zero point

#0001 : 1

PWM0_CH4 period point

#0010 : 2

PWM0_CH4 zero or period point

#0011 : 3

PWM0_CH4 up-count CMPDAT point

#0100 : 4

PWM0_CH4 down-count CMPDAT point

#0101 : 5

Reserved

#0110 : 6

Reserved

#0111 : 7

Reserved

#1000 : 8

PWM0_CH5 up-count CMPDAT point

#1001 : 9

PWM0_CH5 down-count CMPDAT point

End of enumeration elements list.

TRGEN4 : PWM0_CH4 Trigger EADC Enable Bit
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0_CH4 Trigger EADC Disabled

#1 : 1

PWM0_CH4 Trigger EADC Enabled

End of enumeration elements list.

TRGSEL5 : PWM0_CH5 Trigger ADC Source Select\nOthers reserved
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

#0000 : 0

PWM0_CH4 zero point

#0001 : 1

PWM0_CH4 period point

#0010 : 2

PWM0_CH4 zero or period point

#0011 : 3

PWM0_CH4 up-count CMPDAT point

#0100 : 4

PWM0_CH4 down-count CMPDAT point

#0101 : 5

Reserved

#0110 : 6

Reserved

#0111 : 7

Reserved

#1000 : 8

PWM0_CH5 up-count CMPDAT point

#1001 : 9

PWM0_CH5 down-count CMPDAT point

End of enumeration elements list.

TRGEN5 : PWM0_CH5 Trigger EADC Enable Bit
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0_CH5 Trigger EADC Disabled

#1 : 1

PWM0_CH5 Trigger EADC Enabled

End of enumeration elements list.

PWM0_VERSION (VERSION)

PWM0 RTL Design Version Number
address_offset : 0xFFC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

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ChipSelect

PWM0

Peripheral Memory Blocks

Registers

PWM0_CTL0 (CTL0)

PWM0_CLKSRC (CLKSRC)

PWM0_STATUS (STATUS)

PWM0_CLKPSC0_1 (CLKPSC0_1)

PWM0_CLKPSC2_3 (CLKPSC2_3)

PWM0_CLKPSC4_5 (CLKPSC4_5)

PWM0_CNTEN (CNTEN)

PWM0_CAPINEN (CAPINEN)

PWM0_CAPCTL (CAPCTL)

PWM0_CAPSTS (CAPSTS)

PWM0_RCAPDAT0 (RCAPDAT0)

PWM0_FCAPDAT0 (FCAPDAT0)

PWM0_RCAPDAT1 (RCAPDAT1)

PWM0_FCAPDAT1 (FCAPDAT1)

PWM0_RCAPDAT2 (RCAPDAT2)

PWM0_FCAPDAT2 (FCAPDAT2)

PWM0_RCAPDAT3 (RCAPDAT3)

PWM0_FCAPDAT3 (FCAPDAT3)

PWM0_RCAPDAT4 (RCAPDAT4)

PWM0_FCAPDAT4 (FCAPDAT4)

PWM0_RCAPDAT5 (RCAPDAT5)

PWM0_FCAPDAT5 (FCAPDAT5)

PWM0_CNTCLR (CNTCLR)

PWM0_CAPIEN (CAPIEN)

PWM0_CAPIF (CAPIF)

PWM0_PERIOD0 (PERIOD0)

PWM0_SELFTEST (SELFTEST)

PWM0_PBUF0 (PBUF0)

PWM0_PBUF2 (PBUF2)

PWM0_PBUF4 (PBUF4)

PWM0_CMPBUF0 (CMPBUF0)

PWM0_CMPBUF1 (CMPBUF1)

PWM0_CMPBUF2 (CMPBUF2)

PWM0_CMPBUF3 (CMPBUF3)

PWM0_CMPBUF4 (CMPBUF4)

PWM0_CMPBUF5 (CMPBUF5)

PWM0_PERIOD2 (PERIOD2)

PWM0_CTL1 (CTL1)

PWM0_PERIOD4 (PERIOD4)

PWM0_CMPDAT0 (CMPDAT0)

PWM0_CMPDAT1 (CMPDAT1)

PWM0_CMPDAT2 (CMPDAT2)

PWM0_CMPDAT3 (CMPDAT3)

PWM0_CMPDAT4 (CMPDAT4)

PWM0_CMPDAT5 (CMPDAT5)

PWM0_DTCTL0_1 (DTCTL0_1)

PWM0_DTCTL2_3 (DTCTL2_3)

PWM0_DTCTL4_5 (DTCTL4_5)

PWM0_CNT0 (CNT0)

PWM0_CNT2 (CNT2)

PWM0_CNT4 (CNT4)

PWM0_WGCTL0 (WGCTL0)

PWM0_WGCTL1 (WGCTL1)

PWM0_MSKEN (MSKEN)

PWM0_MSK (MSK)

PWM0_BNF (BNF)

PWM0_FAILBRK (FAILBRK)

PWM0_BRKCTL0_1 (BRKCTL0_1)

PWM0_BRKCTL2_3 (BRKCTL2_3)

PWM0_BRKCTL4_5 (BRKCTL4_5)

PWM0_POLCTL (POLCTL)

PWM0_POEN (POEN)

PWM0_SWBRK (SWBRK)

PWM0_INTEN0 (INTEN0)

PWM0_INTEN1 (INTEN1)

PWM0_INTSTS0 (INTSTS0)

PWM0_INTSTS1 (INTSTS1)

PWM0_ADCTS0 (ADCTS0)

PWM0_ADCTS1 (ADCTS1)

PWM0_VERSION (VERSION)