\n
address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
Window Watchdog Timer Reload Counter Register
address_offset : 0x0 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RLDCNT : Window Watchdog Timer Reload Counter Register\nWriting 0x00005AA5 to this register will reload the Window Watchdog Timer counter value to 0x3F.\nNote:This registercan only be written when WWDT counter value between 0 and WINCMP, otherwise WWDT will generate RESET signal.
bits : 0 - 31 (32 bit)
access : write-only
Window Watchdog Timer Counter Value Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNTDAT : WWDT Counter Value\nThis register reflects the current counter value of window watchdog.
bits : 0 - 5 (6 bit)
access : read-only
Window Watchdog Timer Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WWDTEN : Window Watchdog EnableBit\nSet this bit to enable Window Watchdog timer.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Window Watchdog timer function Disabled
#1 : 1
Window Watchdog timer function Enabled
End of enumeration elements list.
PERIODSEL : WWDT Pre-scale Period Select\nThese three bits select the pre-scale for the WWDT counter period.\nPlease refer toTable 6.121WWDT Prescaler Value Selection.
bits : 8 - 11 (4 bit)
access : read-write
WINCMP : WWDT Window Compare Bits\nSet this register to adjust the valid reload window.\nNote:WWDT_RLDCNTregistercan only be written when WWDT counter value between 0 and WINCMP, otherwise WWDT will generate RESET signal.
bits : 16 - 21 (6 bit)
access : read-write
DBGEN : WWDT Debug EnableBit
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
WWDT stopped count if system is in Debug mode
#1 : 1
WWDT still counted even system is in Debug mode
End of enumeration elements list.
Window Watchdog Timer Interrupt Enable Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WWDTIEN : WWDT Interrupt Enable Bit\nSetting this bit will enable the Window Watchdog timer interrupt function.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Watchdog timer interrupt function Disabled
#1 : 1
Watchdog timer interrupt function Enabled
End of enumeration elements list.
Window Watchdog Timer Status Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WWDTIF : WWDT Compare Match Interrupt Flag\nWhen WWCMP matches the WWDT counter, this bit is set to 1. This bit can be cleared by writing '1' to it.
bits : 0 - 0 (1 bit)
access : read-write
WWDTRF : WWDT Reset Flag\nWhen the WWDT counter down counts to 0 or writes WWDT_RLDCNT during WWDT counter larger than WINCMP, chip will be reset and this bit is set to 1. This bit can be cleared by writing '1' to it.
bits : 1 - 1 (1 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.