Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x54 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
RTC Initiation Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT_ACTIVE : RTC Active Status (Read Only)
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
RTC is at reset state
#1 : 1
RTC is at normal active state
End of enumeration elements list.
INIT : RTC Initiation\nWhen RTC block is powered on, RTC is at reset state. User has to write a number (0x a5eb1357) to INIT to make RTC leaving reset state. Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently.\nThe INIT is a write-only field and read value will be always 0.
bits : 1 - 31 (31 bit)
access : read-write
RTC Calendar Loading Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAY : 1-Day Calendar Digit (0~9)
bits : 0 - 3 (4 bit)
access : read-write
TENDAY : 10-Day Calendar Digit (0~3)
bits : 4 - 5 (2 bit)
access : read-write
MON : 1-Month Calendar Digit (0~9)
bits : 8 - 11 (4 bit)
access : read-write
TENMON : 10-Month Calendar Digit (0~1)
bits : 12 - 12 (1 bit)
access : read-write
YEAR : 1-Year Calendar Digit (0~9)
bits : 16 - 19 (4 bit)
access : read-write
TENYEAR : 10-Year Calendar Digit (0~9)
bits : 20 - 23 (4 bit)
access : read-write
RTC 32.768 kHz Oscillator Control Register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LXT_TYPE : LXT TYPE Selection
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Crystal type ( Crystal connect to X32KI with X32KO)
#1 : 1
Oscator illator type ( LXT source from X32KI PIN , X32KO as GPIO
End of enumeration elements list.
X32KO Pin Control Register
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPMODE : GPF0 Operation Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
X32KO (PF.6) is input only mode, without pull-up resistor
#01 : 1
X32KO (PF.6) is output push pull mode
#10 : 2
X32KO (PF.6) is open drain mode
#11 : 3
X32KO (PF.6) is input only mode with internal pull up
End of enumeration elements list.
DOUT : IO Output Data
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
X32KO (PF.6) output low
#1 : 1
X32KO (PF.6) output high
End of enumeration elements list.
CTLSEL : IO Pin State Backup Selection\nWhen low speed 32 kHz oscillator is disabled, X32KO (PF.6) pin can be used as GPIO function. User can program CTLSEL bit to decide X32KO (PF.6) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTOCTL control register.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
X32KO (PF.6) pin I/O function is controlled by GPIO module. It becomes floating when system power is turned off
#1 : 1
X32KO (PF.6) pin I/O function is controlled by VBAT power domain, X32KO (PF.6) pin function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1. I/O pin keeps the previous state after system power is turned off
End of enumeration elements list.
X32KI Pin Control Register
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPMODE : IO Operation Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
X32KI (PF.7) is input only mode, without pull-up resistor
#01 : 1
X32KI (PF.7) is output push pull mode
#10 : 2
X32KI (PF.7) is open drain mode
#11 : 3
X32KI (PF.7) is input only mode with internal pull up
End of enumeration elements list.
DOUT : IO Output Data
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
X32KI (PF.7) output low
#1 : 1
X32KI (PF.7) output high
End of enumeration elements list.
CTLSEL : IO Pin State Backup Selection\nWhen low speed 32 kHz oscillator is disabled, X32KI (PF.7) pin can be used as GPIO function. User can program CTLSEL bit to decide X32KI (PF.7) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTICTL control register.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
X32KI (PF.7) pin I/O function is controlled by GPIO module. It becomes floating state when system power is turned off
#1 : 1
X32KI (PF.7) pin I/O function is controlled by VBAT power domain, X32KI (PF.7) pin function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1. I/O pin keeps the previous state after system power is turned off
End of enumeration elements list.
TAMPER Pin Control Register
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPMODE : IO Operation Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) is input only mode, without pull-up resistor
#01 : 1
TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) is output push pull mode
#10 : 2
TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) is open drain mode
#11 : 3
TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) is input only mode with internal pull up
End of enumeration elements list.
DOUT : IO Output Data
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) output low
#1 : 1
TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) output high
End of enumeration elements list.
CTLSEL : IO Pin State Backup Selection\nWhen tamper function is disabled, TAMPER pin can be used as GPIO function. User can program CTLSEL bit to decide (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_TAMPCTL control register.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) I/O function is controlled by GPIO module. It becomes floating state when system power is turned off
#1 : 1
TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) I/O function is controlled by VBAT power domain. LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8 function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1. I/O pin state keeps previous state after system power is turned off
End of enumeration elements list.
RTC Time Scale Selection Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
_24HEN : 24-hour /12-hour Time Scale Selection\nIndicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
12-hour time scale with AM and PM indication selected
#1 : 1
24-hour time scale selected
End of enumeration elements list.
RTC Day of the Week Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WEEKDAY : Day of the Week Register
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
Sunday
#001 : 1
Monday
#010 : 2
Tuesday
#011 : 3
Wednesday
#100 : 4
Thursday
#101 : 5
Friday
#110 : 6
Saturday
#111 : 7
Reserved
End of enumeration elements list.
RTC Time Alarm Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEC : 1-Sec Time Digit of Alarm Setting (0~9)
bits : 0 - 3 (4 bit)
access : read-write
TENSEC : 10-Sec Time Digit of Alarm Setting (0~5)
bits : 4 - 6 (3 bit)
access : read-write
MIN : 1-Min Time Digit of Alarm Setting (0~9)
bits : 8 - 11 (4 bit)
access : read-write
TENMIN : 10-Min Time Digit of Alarm Setting (0~5)
bits : 12 - 14 (3 bit)
access : read-write
HR : 1-Hour Time Digit of Alarm Setting (0~9)
bits : 16 - 19 (4 bit)
access : read-write
TENHR : 10-hour Time Digit of Alarm Setting (0~2)\nWhen RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication. (If RTC_TIME[21] is 1, it indicates PM time message.)the high bit of TENHR (RTC_TIME[21]) means AM/PM indication.
bits : 20 - 21 (2 bit)
access : read-write
RTC Calendar Alarm Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAY : 1-Day Calendar Digit of Alarm Setting (0~9)
bits : 0 - 3 (4 bit)
access : read-write
TENDAY : 10-Day Calendar Digit of Alarm Setting (0~3)
bits : 4 - 5 (2 bit)
access : read-write
MON : 1-Month Calendar Digit of Alarm Setting (0~9)
bits : 8 - 11 (4 bit)
access : read-write
TENMON : 10-Month Calendar Digit of Alarm Setting (0~1)
bits : 12 - 12 (1 bit)
access : read-write
YEAR : 1-Year Calendar Digit of Alarm Setting (0~9)
bits : 16 - 19 (4 bit)
access : read-write
TENYEAR : 10-Year Calendar Digit of Alarm Setting (0~9)
bits : 20 - 23 (4 bit)
access : read-write
RTC Leap Year Indicator Register
address_offset : 0x24 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LEAPYEAR : Leap Year Indication Register (Read Only)
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
This year is not a leap year
#1 : 1
This year is leap year
End of enumeration elements list.
RTC Interrupt Enable Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALMIEN : Alarm Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTC Alarm interrupt Disabled
#1 : 1
RTC Alarm interrupt Enabled
End of enumeration elements list.
TICKIEN : Time Tick Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTC Time Tick interrupt Disabled
#1 : 1
RTC Time Tick interrupt Enabled
End of enumeration elements list.
SNPDIEN : Snoop Detection Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Snoop detectedinterrupt Disabled
#1 : 1
Snoop detected interrupt Enabled
End of enumeration elements list.
RTC Interrupt Indicator Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALMIF : RTC Alarm Interrupt Flag\nWhen RTC time counters RTC_TIME and RTC_CAL match the alarm setting time registers RTC_TALM and RTC_CALM, this bit will be set to 1 and an interrupt will be generated if RTC Alarm Interrupt enabled ALMIEN (RTC_INTEN[0]) is set to 1. Chip will be waken up if RTC Alarm Interrupt is enabled when chip is at Power-down mode.\nNote: Write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Alarm condition is not matched
#1 : 1
Alarm condition is matched
End of enumeration elements list.
TICKIF : RTC Time Tick Interrupt Flag\nWhen RTC time tick happened, this bit will be set to 1 and an interrupt will be generated if RTC Tick Interrupt enabled TICKIEN (RTC_INTEN[1]) is set to 1. Chip will also be waken up if RTC Tick Interrupt is enabled and this bit is set to 1 when chip is running at Power-down mode.\nNote:Write 1 to clear to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tick condition does not occur
#1 : 1
Tick condition occur
End of enumeration elements list.
SNPDIF : Snoop Detect Interrupt Flag\nWhen tamper pin transition event is detected, this bit is set to 1 and an interrupt is generated if Snoop Detection Interrupt enabled SNPDIEN (RTC_INTEN[2]) is set to1. Chip will be waken up from Power-down mode if spare register snooper detect interrupt is enabled.\nNote:Write 1 to clear this bit.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No snoop event is detected
#1 : 1
Snoop event is detected
End of enumeration elements list.
RTC Time Tick Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TICK : Time Tick Register\nThese bits are used to select RTC time tick period for Periodic Time Tick Interrupt request. \nNote:This register can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
Time tick is 1 second
#001 : 1
Time tick is 1/2 second
#010 : 2
Time tick is 1/4 second
#011 : 3
Time tick is 1/8 second
#100 : 4
Time tick is 1/16 second
#101 : 5
Time tick is 1/32 second
#110 : 6
Time tick is 1/64 second
#111 : 7
Time tick is 1/128 second
End of enumeration elements list.
RTC Time Alarm Mask Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSEC : Mask 1-Sec Time Digit of Alarm Setting (0~9)
bits : 0 - 0 (1 bit)
access : read-write
MTENSEC : Mask 10-Sec Time Digit of Alarm Setting (0~5)
bits : 1 - 1 (1 bit)
access : read-write
MMIN : Mask 1-Min Time Digit of Alarm Setting (0~9)
bits : 2 - 2 (1 bit)
access : read-write
MTENMIN : Mask 10-Min Time Digit of Alarm Setting (0~5)
bits : 3 - 3 (1 bit)
access : read-write
MHR : Mask 1-Hour Time Digit of Alarm Setting (0~9)
bits : 4 - 4 (1 bit)
access : read-write
MTENHR : Mask 10-Hour Time Digit of Alarm Setting (0~2)
bits : 5 - 5 (1 bit)
access : read-write
RTC Calendar Alarm Mask Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDAY : Mask 1-Day Calendar Digit of Alarm Setting (0~9)
bits : 0 - 0 (1 bit)
access : read-write
MTENDAY : Mask 10-Day Calendar Digit of Alarm Setting (0~3)
bits : 1 - 1 (1 bit)
access : read-write
MMON : Mask 1-Month Calendar Digit of Alarm Setting (0~9)
bits : 2 - 2 (1 bit)
access : read-write
MTENMON : Mask 10-Month Calendar Digit of Alarm Setting (0~1)
bits : 3 - 3 (1 bit)
access : read-write
MYEAR : Mask 1-Year Calendar Digit of Alarm Setting (0~9)
bits : 4 - 4 (1 bit)
access : read-write
MTENYEAR : Mask 10-Year Calendar Digit of Alarm Setting (0~9)
bits : 5 - 5 (1 bit)
access : read-write
RTC Spare Functional Control Register
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SNPDEN : Snoop Detection Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
TAMPER pin detection Disabled
#1 : 1
TAMPER pin detection Enabled
End of enumeration elements list.
SNPTYPE0 : Snoop Detection Level\nThis bit controls TAMPER detect event is rising edge or falling edge.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising edge detection
#1 : 1
Falling edge detection
End of enumeration elements list.
SPRRWEN : Spare Register Enable Bit
Note: When spare register is disabled, RTC_SPR0 ~ RTC_SPR4 cannot be accessed
Did not change the content of the spare register, but read data all 0 ..
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Spare register Disabled
#1 : 1
Spare register Enabled
End of enumeration elements list.
SPRCSTS : SPR Clear Flag \nThis bit indicates if the RTC_SPR0 ~RTC_SPR4 content is cleared when specify snoop event is detected.\nWrites 1 to clear this bit.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Spare register content is not cleared
#1 : 1
Spare register content is cleared
End of enumeration elements list.
RTC Access Enable Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RWEN : RTC Register Access Enable Password (Write Only)\nWriting 0xA965 to this register will enable RTC access and keep 1024 RTC clock.\nWriting other vaule will clear RWENF.
bits : 0 - 15 (16 bit)
access : write-only
RWENF : RTC Register Access Enable Flag (Read Only)
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
RTC register read/write Disabled
#1 : 1
RTC register read/write Enabled
End of enumeration elements list.
RTCBUSY : RTC Write Busy Flag
0: RTC write access enable
1: RTC write access disable , RTC under Busy Status.
Note: BUSY By Exceed RTC IP Prcessing Write Counter Capacity ( 6 counts Per 1120 PCLK cycles) .
bits : 24 - 24 (1 bit)
access : read-write
RTC Spare Register 0
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPARE : Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a snooper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register, user should write 0xA965 to RTC_RWEN[15:0] to make sure register read/write enable bit REWNF (RTC_RWEN[16]) is enabled.
bits : 0 - 31 (32 bit)
access : read-write
RTC Spare Register 1
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 2
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 3
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 4
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Frequency Compensation Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQADJ : Frequence Compensation Register
LXT period: the clock period (Hz) of LXT.
bits : 0 - 21 (22 bit)
access : read-write
RTC Time Loading Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEC : 1-Sec Time Digit (0~9)
bits : 0 - 3 (4 bit)
access : read-write
TENSEC : 10-Sec Time Digit (0~5)
bits : 4 - 6 (3 bit)
access : read-write
MIN : 1-Min Time Digit (0~9)
bits : 8 - 11 (4 bit)
access : read-write
TENMIN : 10-Min Time Digit (0~5)
bits : 12 - 14 (3 bit)
access : read-write
HR : 1-Hour Time Digit (0~9)
bits : 16 - 19 (4 bit)
access : read-write
TENHR : 10-hour Time Digit (0~2)\nWhen RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication. (If RTC_TIME[21] is 1, it indicates PM time message.) the high bit of TENHR (RTC_TIME[21]) means AM/PM indication.
bits : 20 - 21 (2 bit)
access : read-write
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