I2C_CTL

I2C_TOCTL

I2C_DAT

I2C_ADDR0

I2C_ADDR1

I2C_ADDRMSK0

I2C_ADDRMSK1

I2C_INTSTS

I2C_CTL2

I2C_STATUS2

I2C_STATUS

I2C_CLKDIV

I2CEN : I2C Function EnableBit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AA : Assert Acknowledge Control Bit
bits : 1 - 1 (1 bit)
access : read-write

STO : I2C STOP Control Bit\nIn Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically.
bits : 2 - 2 (1 bit)
access : read-write

STA : I2C START Command\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
bits : 3 - 3 (1 bit)
access : read-write

SI : I2C Status\nWhen a new state is present in the I2C_STATUS register, if the INTEN bit is set, the I2C interrupt is requested. It must write one by software to this bit after the INTSTS (I2C_INTSTS[0]) is set to 1 and the I2C protocol function will go ahead until the STOP is active or the I2CEN is disabled.\nNote:If software wants to skip clearing INTSTS (I2C_INTSTS[0]), it also can write 1 to SI bit and must set INTEN bit. That INTSTS (I2C_INTSTS[0]) wll be cleared when SI is cleared.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTEN : Interrupt EnableBit
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TOCEN : Time-out Counter Enable Bit\nWhen this bit is set to enabled and clcok be stretched, the 14 bits time-out counter will start counting.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TOCDIV4 : Time-out Counter Input Clock Divider by 4\nWhen enabled, the time-out period is extended 4 times.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DAT : I2C Data\nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port.
bits : 0 - 7 (8 bit)
access : read-write

GC : General Call FunctionControl\nNote: Refer to Address Register section for more detailed information..
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADDR : I2C Salve Address Bits\nThe content of this register is irrelevant when the device is in Master mode. In the Slave mode, the seven most significant bits must be loaded with the device's own address. The device will react if either of the address is matched.
bits : 1 - 7 (7 bit)
access : read-write

ADDRMSK : I2C Slave Address Mask Bits\nI2C bus controllers support multiple address recognition with two address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
bits : 1 - 7 (7 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSTS : I2C STATUS's Interrupt Status\nWhen a new I2C state is present in the I2C_STATUS register, the INTSTS flag is set by hardware. If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested.This bit must be cleared by software writing '1' .\nNote:If software wants to skip clearing INTSTS, it can also write 1 to SI (I2C_CTL [4]) bit and must set INTEN (I2C_CTL [7]) bit. INISTS wll be cleared when SI is cleared.
bits : 0 - 0 (1 bit)
access : read-write

TOIF : Time-out Status\nNote:This bit can be cleared by writing '1' to it.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKAKDONE : Wake-up Address Frame Acknowledge Bit Done\nNote:This bit can be cleared by writing'1' toit.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKUPEN : I2C Wake-up Function EnableBit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OVIEN : I2C Overrun Interrupt Control Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

URIEN : I2C Underrun Interrupt Control Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TWOLVBUF : Two Level Buffer Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NOSTRETCH : I2C BuS Stretch
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATMODE : Data Mode Enable Bit
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSDAT : Master or Slave in Data Mode Enable Control
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKIF : Wake-up Interrupt Flag\nNote:This bit can be cleared by writing '1' toit.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OVIF : I2C Overrun Status Bit\nNote:This bit can be cleared by writing '1' toit.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

URIF : I2C Underrun Status Bit\nNote:This bit can be cleared by writing '1' toit.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WRSTSWK : I2C Read/Write Status Bit in Address Wake-up Frame
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FULL : I2C Two Level Buffer Full
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EMPTY : I2C Two Level Buffer Empty
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUSFREE : Bus Free Status\nThe bus status in the controller.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STATUS : I2C Status Bits (Read Only)
bits : 0 - 7 (8 bit)
access : read-only

DIVIDER : I2C Clock DividedBits\nNote:The minimum value of I2C_CLKDIV is 4.
bits : 0 - 7 (8 bit)
access : read-write