SPI_CTL

SPI_RX0

SPI_RX1

SPI_TX0

SPI_TX1

SPI_PDMACTL

SPI_FIFOCTL

SPI_STATUS

SPI_INTERNAL

SPI_CLKDIV

SPI_SSCTL

GOBUSY : SPI Transfer Control Bit and Busy Status If the FIFO mode is disabled, during the data transfer, this bit keeps the value of '1'. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status. In FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In slave mode, this bit always returns 1 when software reads this register. In master mode, this bit reflects the busy or idle status of SPI. Note: 1.When FIFO mode is disabled, all configurations should be set before writing 1 to the GOBUSY bit in the SPI_CTL register. 2. When FIFO bit is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA controller finishes the data transfer.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXNEG : Receiveon Negative Edge\nNote: Refer to Edge section.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXNEG : Transmit on Negative Edge\nNote: Refer to Edge section.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

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DWIDTH : Data Width\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can be up to 32 bits.
bits : 3 - 7 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LSB : Send LSB First\nNote: Refer to LSB first section.
bits : 10 - 10 (1 bit)
access : read-write

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CLKPOL : Clock Polarity\nNote: Refer to Clock Parity section.
bits : 11 - 11 (1 bit)
access : read-write

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SUSPITV : Suspend Interval (Master Only)
bits : 12 - 15 (4 bit)
access : read-write

UNITIEN : Unit Transfer Interrupt Enable Bit
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SLAVE : Slave Mode Selection\nNote: Refer to Slave Selection section
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

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REORDER : Byte Reorder Function EnableBit\nNote: The suspend interval is defined in SUSPITV.Refer to Byte Reorder section.\nNote: Byte Suspend is only used in SPI Byte Reorder mode.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

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FIFOM : FIFO Mode EnableBit\nNote: Refer to FIFO Mode section.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

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TWOBIT : 2-bit Transfer Mode Enable Bit\nRefer to Two Bit Transfer Mode section\nNote: automatically
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

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DUALDIR : Dual I/O Mode Direction Control\nRefer to Dual I/O Mode section.
bits : 28 - 28 (1 bit)
access : read-write

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DUALIOEN : Dual I/O Mode EnableBit\nRefer to Dual I/O Mode section.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKSSEN : Wake-up by Slave Select EnableBit\nNote: The Slave select wake-up function is only available in SPI Slave mode. When the system enters Power-down mode, the system can be wake-up from the SPI controller if this bit is enabled and there is any toggle on the SPI_SS port. After the system wake-up, this bit must be cleared by user to disable the wake-up requirement.
bits : 30 - 30 (1 bit)
access : read-write

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WKCLKEN : Wake-up by SPI Clock EnableBit\nNote: When the system enters Power-down mode, the system can be wake-up from the SPI controller if this bit is enabled and there is any toggle on the SPI_CLK port. After the system wake-up, this bit must be cleared by user to disable the wake-up requirement.
bits : 31 - 31 (1 bit)
access : read-write

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End of enumeration elements list.

RX : Receive Data Register (Read Only)\nThe received data can be read on it. If the FIFO bit is set as 1, the user also checks the RXEMPTY, SPI_STATUS[0], to check if there is any more received data or not.\nNote:The SPI_RX1 is used only in TWOBIT bit (SPI_CTL[22])is set 1. The first channel's received data shall be read from SPI_RX0 and the second channel's received data shall be read from SPI_RX1 in two-bit mode. SPI_RX0 shall be read first in TWOBIT mode.\nIn FIFO and two-bit mode, the first read back data in SPI_RX0 is the first channel data and the second read back data in SPI_RX0 is the second channel data.
bits : 0 - 31 (32 bit)
access : read-only

TX : Transmit Data Register (Write Only)\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register.\nFor example, if DWIDTH is set to 0x8, the bit SPI_TX[7:0] will be transmitted in next transfer. If DWIDTH is set to 0x0, the SPI controller will perform a 32-bit transfer.\nNote:\n1. The SPI_TX1 is used only when TWOBIT bit (SPI_CTL[22])is set 1. The first channel's transmitted data shall be written into SPI_TX0 and the second channel's transmitted data shall be written into SPI_TX1 in two-bit mode. SPI_TX0 shall be written first in TWOBIT mode.\nIn FIFO and two-bit mode, the first written into data in SPI_TX0 is the first channel's transmitted data and the second written data in SPI_TX1 is the second channel's transmitted data.\n2.If the SPI controller operates as slave device and FIFO mode is disabled, software must update the transmit data register before setting the GOBUSY bit to 1.
bits : 0 - 31 (32 bit)
access : write-only

TXPDMAEN : Transmit PDMA Enable Bit\nRefer to PDMA section for more detailed information.\nSPI_CTLNote:\n1. Two transaction need minimal 18 APB clock + 8 SPI peripheral clocks suspend interval in master mode for edge mode and 18 APB clock + 9.5 SPI peripheral clocks for level mode.\n2. If the 2-bit function is enabled, the requirement timing shall append 18 APB clock based on the above clock period.\nHardware will clear this bit to 0 automatically after PDMA transfer is done.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXPDMAEN : Receiving PDMA EnableBit Refer to PDMA section for more detail information. Note: Hardware will clear this bit to 0 automatically after PDMA transfer done. In Slave mode and the FIFO bit is disabled, if the receive PDMA is enabled but the transmit PDMA is disabled, the minimal suspend interval between two successive transactions input is need to be larger than 9 SPI peripheral clock + 4 APB clock for edge mode and 9.5 SPI peripheral clock + 4 APB clock.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMARST : PDMA Reset It is used to reset the SPI PDMA function into default state. Note:It is auto cleared to 0 after the reset function has done.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXFBCLR : Receive FIFO Buffer Clear Note:This bit is used to clear the receiver counter in FIFO Mode. This bit can be written 1 to clear the receiver counter and this bit will be cleared to 0 automatically after clearing receiving counter. After the clear operation, the flag of RXEMPTY in SPI_STATUS[0] will be set to 1 .
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXFBCLR : Transmit FIFO Buffer Clear Note:This bit is used to clear the transmit counter in FIFO Mode. This bit can be written 1 to clear the transmitting counter and this bit will be cleared to 0 automatically after clearing transmitting counter. After the clear operation, the flag of TXEMPTY in SPI_STATUS[2] will be set to 1 .
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXTHIEN : Receive Threshold Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

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TXTHIEN : Transmit Threshold Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : read-write

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RXOVIEN : ReceiveFIFO Overrun Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

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RXTOIEN : RX Read Time Out Interrupt Enable Bit
bits : 7 - 7 (1 bit)
access : read-write

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RXTH : Received FIFO Threshold\nIf RX valid data counts are greater than RXTH, RXTHIF (SPI_STATUS[8])will be set to 1..
bits : 24 - 26 (3 bit)
access : read-write

TXTH : Transmit FIFO Threshold\nIf TX valid data counts are smaller than or equal to TXTH, TXTHIF(SPI_STATUS[10])will be set to 1.
bits : 28 - 30 (3 bit)
access : read-write

RXEMPTY : Receive FIFO Buffer Empty Indicator(Read Only)
bits : 0 - 0 (1 bit)
access : read-only

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RXFULL : Receive FIFO Buffer Full Indicator(Read Only)
bits : 1 - 1 (1 bit)
access : read-only

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TXEMPTY : Transmit FIFO Buffer Empty Indicator(Read Only)
bits : 2 - 2 (1 bit)
access : read-only

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TXFULL : Transmit FIFO Buffer Full Indicator (Read Only)
bits : 3 - 3 (1 bit)
access : read-only

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LTRIGF : Level Trigger Accomplish Flag(Read Only)\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done.\nNote: This bit is READ only. As the software sets the GOBUSY bit to 1, the LTRIGF will be cleared to 0 after 4 SPI peripheral clock periods plus 1 system clock period. In FIFO mode, this bit is unmeaning.
bits : 4 - 4 (1 bit)
access : read-only

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End of enumeration elements list.

SLVSTAIF : Slave Start Interrupt Flag\nIt is used to dedicate that the transfer has started in Slave mode with no slave select.
bits : 6 - 6 (1 bit)
access : read-write

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UNITIF : Unit Transfer Interrupt Flag Note 2: This bitcan be cleared by writing 1 to it.
bits : 7 - 7 (1 bit)
access : read-write

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End of enumeration elements list.

RXTHIF : RX FIFO Threshold Interrupt Flag(Read Only)
bits : 8 - 8 (1 bit)
access : read-only

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RXOVIF : Receive FIFO Overrun Interrupt Flag\nNote 1: If SPI receives data when RX FIFO is full, this bit will set to 1, and the received data will be dropped.\nNote 2: This bit will be cleared by writing 1 to it.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXTHIF : Transmit FIFO Threshold Interrupt Flag(Read Only)
bits : 10 - 10 (1 bit)
access : read-only

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RXTOIF : Receive Time-outInterrupt Flag\nRefer to Time Out section.\nNote: This bit will be cleared by writing 1 to it.
bits : 12 - 12 (1 bit)
access : read-write

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End of enumeration elements list.

SLVTOIF : Slave Time-out Interrupt Flag\nIf SLVTOIEN (SPI_SSCTL[6]) is set to 1, this bit will be asserted when slave time-out event occur. Software can clear this bit by setting RXFBCLR (SPI_FIFOCTL[0]) or writing 1 to clear this bit.
bits : 13 - 13 (1 bit)
access : read-write

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End of enumeration elements list.

SLVTXSKE : Slave Mode Transmit Skew Buffer Empty Status\nThis bit indicates the empty status of transmit skew buffer which is used in Slave mode.
bits : 15 - 15 (1 bit)
access : read-write

RXCNT : Receive FIFO Data Counts (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer.
bits : 16 - 19 (4 bit)
access : read-only

TXCNT : Transmit FIFO Data Counts (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer.
bits : 20 - 23 (4 bit)
access : read-only

WKSSIF : Wake-up by Slave Select Interrupt Flag\nWhen chip is woken up from Power-down mode by the toggle event on SPI_SS port, this bit is set to 1. This bit can be cleared by writing '1' to it.
bits : 30 - 30 (1 bit)
access : read-write

WKCLKIF : Wake-up by SPI Clock Interrupt Flag\nWhen chip is woken up from Power-down mode by the toggle event on SPI_CLK port, this bit is set to 1. This bit can be cleared by writing '1' to it.
bits : 31 - 31 (1 bit)
access : read-write

DIVIDER : Clock Divider\nThe value is the 1th frequency divider of the PCLK to generate the serial clock of SPI_SCLK. The desired frequency is obtained according to the following equation:\nWhere\n is the SPI peripheral clock source. It is defined in the CLK_SEL2[21:20] in Clock control section (CLK_BA + 0x18).
bits : 0 - 7 (8 bit)
access : read-write

SS : Slave SelectionControl (Master Only) If AUTOSS bit (SPI_SSCTL[3]) is cleared, writing 1 to SS[0] (SPI_CTL[0]) bit sets the SPI_SS0 line to an active state and writing 0 sets the line back to inactive state(the same as SPI_CTL[1] for SPI_SS1). Note: 1. This interface can only drive one device/slave at a given time. Therefore, the slaves select of the selected device must be set to its active level before starting any read or write transfer. 2. SPI_SS0 is also defined as device/slave select input in Slave mode. And that the slave select input must be driven by edge active trigger which level depend on the SSACTPOL setting, otherwise the SPI slave core will go into dead path until the edge active triggers again or reset the SPI core by software.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

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SSACTPOL : Slave Selection Active Polarity\nIt defines the active polarity of slave selection signal (SPI_SS[1:0]).
bits : 2 - 2 (1 bit)
access : read-write

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End of enumeration elements list.

AUTOSS : Automatic Slave Selection Function Enable Bit (Master Only)
bits : 3 - 3 (1 bit)
access : read-write

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End of enumeration elements list.

SSLTRIG : Slave Select Level Trigger Control
bits : 4 - 4 (1 bit)
access : read-write

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SLV3WIRE : Slave 3-wire Mode Enable Bit This bit is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPI_CLK, SPI_MISO, and SPI_MOSI when it is set as a slave device. Note 1:Refer to No Slave Select Mode. Note 2: In no slave select signal mode, hardware will set the SSLTRIG (SPI_SSCTL[4]) as 1 automatically.
bits : 5 - 5 (1 bit)
access : read-write

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End of enumeration elements list.

SLVTOIEN : Slave Time-out Interrupt Enable Bit\nThis bit is used to enable the slave time-out function in slave mode and there will be an interrupt if slave time-out event occur
bits : 6 - 6 (1 bit)
access : read-write

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End of enumeration elements list.

SLVABORT : Abort in Slave Mode with No Slave Selected Refer to No Slave Select Mode. Note: It is auto cleared to 0 by hardware when the abort event is active.
bits : 8 - 8 (1 bit)
access : read-write

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SSTAIEN : Slave Start Interrupt EnableBit\nRefer to No Slave Select Mode.
bits : 9 - 9 (1 bit)
access : read-write

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SSINAIEN : Slave Select Inactive Interrupt Enable Bit\nIt is used to enable the interrupt when the transfer has done in slave mode.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SLVTOCNT : Slave Mode Time-out Period\nIn Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active. The clock source of the time-out counter is Slave peripheral clock. If the value is 0, it indicates the slave mode time-out function is disabled.
bits : 20 - 29 (10 bit)
access : read-write