DSRC_CTL (CTL)

DSRC_CRCSEED (CRCSEED)

DSRC_RBCNT (RBCNT)

DSRC_CHKSUM (CHKSUM)

DSRC_TX (TX)

DSRC_CTL2 (CTL2)

DSRC_TXR (TXR)

DSRC_RXR (RXR)

DSRC_ICR (ICR)

DSRC_RX (RX)

DSRC_TMR2 (TMR2)

DSRC_TMR3 (TMR3)

DSRC_INTEN (INTEN)

DSRC_TMR4 (TMR4)

DSRC_STATUS (STATUS)

DSRC_PREAMBLE (PREAMBLE)

DSRCEN : DSRC Enable Bit\nNote: When DSRC is enabled, SPI1 will set SUSPITV (SPI_CTL[15:12]), DWIDTH (SPI_CTL[7:3]), REORDER (SPI_CTL[19]), FIFOM (SPI_CTL[21]), TWOBIT (SPI_CTL[22]), and DUALIOEN (SPI_CTL[29]) set as 0x0, 0x8, 0, 1, 0, and 0 automatically for data byte transaction in DSRC application.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SWRXEN : Software Control RX_ON Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CODECEN : CODEC Enable Bit\nNote: When both DSRCEN and CODECEN are enabled, the SPI1 will set TXNEG (SPI_CTL[2]), RXNEG (SPI_CTL[1]), CLKPOL (SPI_CTL[11]), SS (SPI_SSCTL[1:0]), SSACTPOL (SPI_SSCTL[2]), AUTOSS (SPI_SSCTL[3]) and SLV3WIRE (SPI_SSCTL[5]) as 0, 1, 0, 0x1, 1, 1, and 1 automatically for FM0 (or Manchester) CODEC communication. In this codition, SPI1 will set the SLAVE (SPI_CTL[18]) bit automatically and operate as Master mode in data transmitting phase and Slave 3-wired mode in data receiving phase automatically.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CODECFMT : CODEC Format Select Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRDETEN : Bit Rate Detection Enable Bit \nNote: This function is only for FM0 CODEC.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRATEMOD : Bit Rate Error Mode
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRCEN : CRC Engine Enable Bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRCMSB : CRC Generation on Data MSB\nNote: If the input data is 0xaa, the sequence of CRC bit generation is 01010101 when the bit is set as 0. Otherwise, the sequence of CRC bit generation is 10101010 when the bit is set as 1.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHKSREV : Checksum Reverse\nNote: If the checksum data is 0XDD7B0F2E, the bit order reversed for CRC checksum is 0x74F0DEBB.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHKSFMT : Checksum Format
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SEEDM : CRC Seed Mode
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PREAMFMT : Preamble Pattern Format\nNote: It is MSB first to be sent.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDRXDIS : Power-down Mode RXON Disable Bit
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKHXTEN : Wake-up HXT Clock Enable Bit \nSetting this bit to 1 enables RF wake-up HXT clock.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TBPEN : TBP Enable Bit\nSetting this bit to 1 enables TBP operation.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRANSFIN : TBP Transfer Done\nWhen the TTDMAEN (DSRC_CTL[20]) is disabled and the transmitted data is written into DSRC_TX by user, this bit shall be set into the TBP to terminate the processor before the last the transmitted data. The minimum length of transmitted data is 2 bytes.\nNote: This bit will be cleared after the TTBP transfer is done.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TTDMAEN : TBP Transmit DMA Enable Bit
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRDMAEN : TBP Receive DMA Enable Bit
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRCBSWAP : CRC BYTE SWAP
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FORCETX : Force TX State Control Bit\nNote: This bit will be cleared automatically
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FORCERX : Force RX State Control Bit\nNote: This bit will be cleared automatically.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXON : RX_ON Control Bit
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKPOL : Wake-up Pin Polarity Control Bit
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRATEACC : Bit Rate Accuracy Control Bits\nPlease refer to Table 6.181.\nNote: This function is only for FM0 CODEC.
bits : 28 - 30 (3 bit)
access : read-write

CRCSEED0 : The CRC Seed Initial Pattern 0\nThe bits field indicates the CRC seed initial pattern 0 of DSRC.\nFor receiver:\nThe CRC will be calculated by the initial value. The TBP will auto compare the calculated result with the received CRC data and report its compare result into CRC0_OK (DSRC_STATUAS[24])\nFor Transmit:\nThe bit field is used to generate the CRC when the SEEDM (DSRC_CTL[20]) is set to 0.
bits : 0 - 15 (16 bit)
access : read-write

CRCSEED1 : The CRC Seed Initial Pattern 1\nThe bit field indicates the CRC seed initial pattern 1 of DSRC.\nFor receiver:\nThe CRC will be calculated by the initial value. The TBP will auto compare the calculated result with the received CRC data and report its compare result into CRC1_OK (DSRC_STATUAS[25])\nFor transmitter:\nThe bit field is used to generate the CRC when the SEEDM (DSRC_CTL[20]) is set to 1.
bits : 16 - 31 (16 bit)
access : read-write

TBPBCNT : TBP Receive Byte Count\nThe bits field indicates the number of receive byte count on RTBP when the CRCCOR (DSRC_STATUS[0]) is set to 1 and the STPFRM(DSRC_STATUS[3]) is set to 1. Otherwise, the value is 0.\nNote 1: The 2 bytes CRC is not calculated in this field.\nNote 2: If there is CRC calculation check error, the value will be cleared by hardware to calculate the next incoming data stream.
bits : 0 - 8 (9 bit)
access : read-only

CHECKSUM0 : The CRC Checksum0\nThe bit field indicates the CRC checksum of the initial value is CHKSUM0 (DSRC_CHKSUM[15:0]).
bits : 0 - 15 (16 bit)
access : read-only

CHECKSUM1 : The CRC Checksum1\nThe bit field indicates the CRC checksum of the initial value is CHKSUM1 (DSRC_CHKSUM[31:16])
bits : 16 - 31 (16 bit)
access : read-only

TX : TBP Transmit Data\nThe bit field indicates the transmitted data on the TBP before being transmitted to TTBP.
bits : 0 - 7 (8 bit)
access : write-only

SOFNUM : Start of Frame Number for Transmission\nThis bit field is used to define the number of SOF packet which is repeated send in the SPI bus before the transmitted data.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CODECDEGSEL : FM0 CODEC Deglitch Selection\nThis bits field is used to define how much width of glitch would be filtered.
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXDATR : Transmit Data After TTBP \nThe bits field indicates the transmitted data after the TTBP. When the 8-Bit transmitted data is processed by the TTBP, the register indicates the processed content.
bits : 0 - 7 (8 bit)
access : read-only

RXDATR : Receive Data Before RTBP \nThe bits field indicates the current receive data before the RTBP (It comes from the SPI RX buffer). Before the 8-Bit is processed by the RTBP, the register indicates the un-processed content.
bits : 0 - 7 (8 bit)
access : read-only

RX : TBP Receiver Data\nThe bit field indicates the received data on the TBP after the RTBP.
bits : 0 - 7 (8 bit)
access : read-only

CMPDAT : Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the CNTIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will be set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT, or the core will run into unknown state.
bits : 0 - 23 (24 bit)
access : read-write

PSC : Prescale Counter
bits : 24 - 31 (8 bit)
access : read-write

CMPDAT : Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the CNTIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will be set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT, or the core will run into unknown state.
bits : 0 - 23 (24 bit)
access : read-write

PSC : Prescale Counter
bits : 24 - 31 (8 bit)
access : read-write

CRCCORIE : CRC Check Correct Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRCERRIE : CRC Error Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STRFRMIE : Start Field of Frame Detection Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STPFRMIE : Stop Field of Frame Detection Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXDATERRIE : Received Data Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRATERRIE : Bit Rate Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTBPDIE : TBP Byte Receive Done Interrupt Enable Bit
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXDONEIE : Transmit Data Done Interrupt Enable Bit
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

T2TOIE : Timer 2 Time-out Interrupt Enable Bit
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

T3TOIE : Timer 3 Time-out Interrupt Enable Bit
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

T4TOIE : Timer 4 Time-out Interrupt Enable Bit
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EPWKIE : External Pin Wake-up Interrupt Enable Bit
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPDAT : Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the CNTIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will be set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT, or the core will run into unknown state.
bits : 0 - 23 (24 bit)
access : read-write

PSC : Prescale Counter
bits : 24 - 31 (8 bit)
access : read-write

CRCCOR : CRC CorrectBit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRCERR : CRC Error Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STRFRM : Start Field of Frame Detection Flag\nThis flag indicates start field of frame is detected.\nNote: Write 1 to clear this flag.
bits : 2 - 2 (1 bit)
access : read-write

STPFRM : Stop Field of Frame Detection Flag\nThis flag indicates stop field of frame is detected.\nNote: Write 1 to clear this flag.
bits : 3 - 3 (1 bit)
access : read-write

RXDATERR : Received Data Error Flag\nNote: Write 1 to clear this flag.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRATERR : Bit Rate Error Flag\nThis flag indicates FM0 or MANCHESTER bit rate error depending on CODECFMT (DSRC_CTL[3]) setting if BRDETEN (DSRC_CTL[4]) is set to 1.\nNote: Write 1 to clear this flag.
bits : 5 - 5 (1 bit)
access : read-write

TTBPDONE : TBP Byte Transfer Done\nNote 1: This bit is automatically cleared by TBP_TXDMA_ACK when the TTDMAEN (DSRC_CTL[18]) is set or by the write signal of DSRC_TX register when the TTDMAEN (DSRC_CTL[18]) is not set.\nNote 2: If the TTDMAEN (DSRC_CTL[18]) is not set, the first TTBPDONE is set after the TTBP module send out the PREAMBLE and Head 7E patterns. The first transmitted data shall be written into the TX (DSRC_TX) after this flag is set.\nNote 3: After the TRANFIN (DSRC_CTL[17]) is set, this bit won't report the byte transfer done status again. The user shall check the TXDONE (DSRC_STATUS[12]) to know the current transfer has done both on the TTBP and SPI device.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTBPDONE : TBP Byte Receive Done\nNote: This bit is automatically cleared by TBP_RXDMA_ACK when the TRDMAEN (DSRC_CTL[19]) is set or by the read signal of DSRC_RX register when the TRDMAEN (DSRC_CTL[19]) is not set.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXFINISH : TX Transfer Finish\nNote:Write 1 to clear this flag.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TTBPFULL : TTBPTransmit Full\nNote: If the TTDMAEN (DSRC_CTL[18] is disabled, the transmitted data can be written into the DSRC_TX register when the TTBPDONE (DSRC_STATUS[8]) is set to 1 and the TTBPFULL must be set as 0. Otherwise, the TTBP transmit done flag TTBPDONE (DSRC_STATUS[8]) won't be active in next data.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

T2TO : Timer 2 Time-out Flag\nThis flag is set after the Timer Controller finishes counting the value set by DSRC_TMR2.\nNote1: The Timer Counter is started when DSRC wake-up and the counter is cleared when the Start of Frame is detected before T2TO event is set.\nNote2: Write 1 to clear this flag.
bits : 18 - 18 (1 bit)
access : read-write

T3TO : Timer 3 Time-out Flag\nThis flag is set after the Timer Controller finishes counting the value set by DSRC_TMR3.\nNote1: The Timer Counter is startedwhen the Start of Frame is detected and the counter is cleared when the Stop of Frame is detect before the T3TO event is set.\nNote2: Write 1 to clear this flag.
bits : 19 - 19 (1 bit)
access : read-write

T4TO : Timer 4 Time-out Flag\nThis flag is set after the Timer Controller finishes counting the value set by DSRC_TMR4.\nNote1: The Timer Counter is started when SPI detected the Stop of Frame and DSRC CRC correct flag is active.\nNote2: Write 1 to clear this flag.
bits : 20 - 20 (1 bit)
access : read-write

CRC0_OK : CRC0 Compare OK\nNote: Writing1 to CRCCOR (DSRC_STATUS[0]), CRCERR (DSRC_STATUS[1]) and itself can clear this flag.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRC1_OK : CRC1 Compare OK\nNote: Writing1 to CRCCOR (DSRC_STATUS[0]), CRCERR (DSRC_STATUS[1]) and itself can clear this flag.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EPWKF : External Pin Wake-up Event Flag\nNote: Write 1 to clear this flag.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PREPAT : The Preamble Pattern\nThe bit field indicates the preamble pattern of DSRC. If the PREAMFMT (DSRC_CTL[24]) is set to 1, 32-bit preamble pattern is transmitted and the transmitted sequence is PREPAT[31:24], PREPAT[23:16], PREPAT[15:8] and PREPAT[7:0].\nIf the PREAMFMT (DSRC_CTL[24]) is set to 0, 16-bit preamble pattern is transmitted and the transmitted sequence is PREPAT[15:8] and PREPAT[7:0].
bits : 0 - 31 (32 bit)
access : read-write