ADC_DAT0 (DAT0)

ADC_DAT4 (DAT4)

ADC_DAT5 (DAT5)

ADC_DAT6 (DAT6)

ADC_DAT7 (DAT7)

ADC_DAT12 (DAT12)

ADC_DAT13 (DAT13)

ADC_DAT14 (DAT14)

ADC_DAT15 (DAT15)

ADC_DAT1 (DAT1)

ADC_DAT16 (DAT16)

ADC_DAT17 (DAT17)

ADC_CTL (CTL)

ADC_CHEN (CHEN)

ADC_CMP0 (CMP0)

ADC_CMP1 (CMP1)

ADC_STATUS (STATUS)

ADC_PDMA (PDMA)

ADC_PWD (PWD)

ADC_CALCTL (CALCTL)

ADC_CALWORD (CALWORD)

ADC_EXTSMPT0 (EXTSMPT0)

ADC_EXTSMPT1 (EXTSMPT1)

ADC_DAT2 (DAT2)

ADC_DAT3 (DAT3)

RESULT : A/D Conversion Result\nThis field contains conversion result of ADC.
bits : 0 - 11 (12 bit)
access : read-only

VALID : Valid Flag\nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DATx register is read.
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

OV : Overrun Flag\nIf converted data in RESULT (ADC_DAT[11:0]) has not been read before the new conversion result is loaded to this register, OVis set to 1. It is cleared by hardware after the ADC_DATx register is read.
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ADCEN : A/D Converter EnableBit\nNote: Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit to save power consumption.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCIEN : A/D Interrupt EnableBit\nA/D conversion end interrupt request is generated if ADCIEN(ADC_CTL[1]) bit is set to 1.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADMD : A/D Converter Operation Mode
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HWTRGSEL : Hardware Trigger Source Select Bit\nIn hardware trigger mode, ADC starts to convert by the external trigger from STADC pin or PWM trigger.\nNote:Software should disable HWTRGEN (ADC_CTL[8]) and clear SWTRG (ADC_CTL[11]) before change HWTRGSEL (ADC_CTL[5:4]).
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HWTRGCOND : Hardware External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HWTRGEN : Hardware External Trigger EnableBit\nEnable or disable triggering of A/D conversion by external STADC pin. If external trigger is enabled, ADC starts to convert by the selected hardware trigger source.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PTEN : PDMA Transfer EnableBit\nWhen A/D conversion is completed, the converted data is loaded into ADC_DATx, software can enable this bit to generate a PDMA data transfer request.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIFF : Differential Mode Selection\nNote: Calibration should calibrated each time when switching between single-ended and differential mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SWTRG : Software Trigger A/D Conversion Start\nADC can be start to convert from three sources: software write, external pin STADC and PWM trigger. SWTRG(ADC_CTL[11]) is cleared to 0 by hardware automatically at the end of single mode and single-cycle scan mode on specified channels. In continuous scan mode, A/D conversion is continuously performed sequentially unless software writes 0 to this bit or chip reset.\nNote: After ADC conversion is done, SW needs to wait at least one ADC clock before to set this bit high again.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMSEL : Select A/D Enable Time-out Source\nSelects one of four timer events sourceto trigger ADC starts to convert.
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMTRGMOD : Timer Event Trigger ADC Conversion Mode\nNote1: setting TMSEL (ADC_CTL[13:12]) to select timer event from timer0~3.\nNote2:If timer event is used as ADC trigger source, ADCEN (ADC_CTL[0]) needs to be disabled.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REFSEL : Reference Voltage Source Selection
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RESSEL : Resolution Selection
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMPDMACNT : Timer Event PDMA Count\nWhen each timer event occur PDMA will transfer TMPDMACNT +1 ADC result in the amount of this register setting.\nNote: The total amount of PDMA transferring data should be set in PDMA byte count register. When PDMA finish is set, ADC will not be enabled and will start transfer even though the timer event occurred.
bits : 24 - 31 (8 bit)
access : read-write

CHEN0 : Analog Input Channel 0 Enable Bit (Convert Input Voltage From PA.0)\nNote:If software enables more than one channel, the channel with the smallest number will be selected and the other enabled channels will be ignored.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN1 : Analog Input Channel 1 EnableBit (Convert Input Voltage From PA.1)
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN2 : Analog Input Channel 2 EnableBit (Convert Input Voltage From PA.2)
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN3 : Analog Input Channel 3 EnableBit (Convert Input Voltage From PA.3)
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN4 : Analog Input Channel 4 EnableBit (Convert Input Voltage From PA.4)
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN5 : Analog Input Channel 5 EnableBit (Convert Input Voltage From PA.5)
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN6 : Analog Input Channel 6 EnableBit (Convert Input Voltage From PA.6)
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN7 : Analog Input Channel 7 EnableBit (Convert Input Voltage From PA.7)
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN12 : Analog Input Channel 12 Enable Bit (Convert VBG)
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN13 : Analog Input Channel 13 Enable Bit (Convert VBAT)
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN14 : Analog Input Channel 14 EnableBit (Convert VTEMP)
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN15 : Analog Input Channel 15 EnableBit (Convert Int_VREF)
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN16 : Analog Input Channel 16 EnableBit (Convert AVDD)
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN17 : Analog Input Channel 17 EnableBit (ConvertAVSS)
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCMPEN : A/D Compare EnableBit\nSet 1 to this bit to enable comparing CMPDAT (ADC_CMPx[27:16]) with specified channel conversion results when converted data is loaded into the ADC_DATx register.\nNote:When this bit is set to 1 and CMPMCNT (ADC_CMPx[11:8]) is 0, the ADCMPFx (ADC_STATUS[2:1]) will be set once the match is hit.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCMPIE : A/D Compare Interrupt EnableBit\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND (ADC_CMPx[2]) and CMPMCNT (ADC_CMPx[11:8]), ADCMPFx(ADC_STATUS[2:1]) bit will be asserted, in the meanwhile, if ADCMPIE(ADC_CMPx[1]) is set to 1, a compare interrupt request will generate.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPCOND : Compare Condition\nNote: When the internal counter reaches the value to (CMPMATCNT +1), the ADCMPFx (ADC_STATUS[2:1]) bit will be set.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPCH : Compare Channel Selection\nSet this field to select which channel's result to be compared.\nNote: Valid setting of this field is channel 0~17, but channel 8~12 are reserved.
bits : 3 - 7 (5 bit)
access : read-write

CMPMCNT : Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND (ADC_CMPx[2]), the internal match counter will increase 1. \nNote:When the internal counter reaches the value to (CMPMCNT+1), the ADCMPFx (ADC_STATUS[2:1]) bit will be set.
bits : 8 - 11 (4 bit)
access : read-write

CMPDAT : Comparison Data\nThe 12 bits data is used to compare with conversion result of specified channel. Software can use it to monitor the external analog input pin voltage variation in scan mode without imposing a load on software.
bits : 16 - 27 (12 bit)
access : read-write

ADIF : A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion, ADIF (ADC_STATUS[0]) is set to 1 at these two conditions:\nWhen A/D conversion ends in single mode\nWhen A/D conversion ends on all specified channels in scan mode.\nNote: This bit can be cleared to 0 by software writing 1.
bits : 0 - 0 (1 bit)
access : read-write

ADCMPF0 : A/D Compare Flag0\nWhen the selected channel A/D conversion result meets the setting condition in ADC_CMP0, this bit is set to 1.\nThis flag can be cleared by writing 1 to it.\nNote: This flag can be cleared by software writing 1 to it, when this flag is set, the matching counter will be reset to 0,and continue to count when user writes 1 to clear ADCMPF0 (ADC_STATUS[1]).
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCMPF1 : A/D Compare Flag1\nWhen the selected channel A/D conversion result meets the setting condition in ADC_CMP1, this bit is set to 1.\nNote: This flag can be cleared by software writing 1 to it, when this flag is set, the matching counter will be reset to 0,and continue to count when user writes 1 to clear ADCMPF1 (ADC_STATUS[2]).
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUSY : BUSY/IDLE(Read Only)\nNote:This bit is mirror of SWTRG (ADC_CTL [11]) bit.
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CHANNEL : Current Conversion Channel(Read Only)
bits : 4 - 8 (5 bit)
access : read-only

INITRDY : ADC Initial Ready by Power-up Sequence Completed\nNote: This bit will be set after system reset occurred and automatically cleared by power-up event.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AD_PDMA : ADC PDMA Current Transfer Data(Read Only)\nDuring PDMAtransfer, reading these bits can monitor the current PDMA transfer data.
bits : 0 - 11 (12 bit)
access : read-only

PWUPRDY : ADC Power-up Sequence Completed and Ready for Conversion
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWDCALEN : Power Up Calibration Function EnableBit\nNote:This bit works together with CALSEL (ADC_CALCTL[3]),see the following\n{PWDCALEN,CALFBSEL}Description:\nPWDCALEN is 0 and CALFBSEL is 0: No need to calibrate. \nPWDCALEN is 0 and CALFBSEL is 1: No need to calibrate.\nPWDCALEN is 1 and CALFBSEL is 0: Load calibration word when power up.\nPWDCALEN is 1 and CALFBSEL is 1: Calibrate when power up.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWDMOD : ADC Power Saving Mode\nSet this bit fields to select ADC power saving mode.\nNote1: Different power saving mode has different power down/up sequence.To avoid ADC powering up with wrong sequence, user must keep PWMOD (ADC_PWD[3:2]) consistent each time in power down and power up. \nNote2:While the ADC is powered up from power saving mode (set to 00b/01b/11b) without calibration, the PWDCALEN(ADC_PWD[1]) is set to 0, and the calibration value will be reset.
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CALEN : Calibration Function EnableBit\nEnable this bit to turn on the calibration function block.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CALSTART : Calibration Functional Block Start
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CALDONE : Calibrate Functional Block Done\nNote:This bit is set by hardware and auto cleard by hardware, This bit can also be cleared by software writing 1.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CALSEL : Calibration Functional Block Selection
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CALWORD : Calibration Word Bits Write to this register with the previous calibration word before load calibration action, read this register after calibration done. Note:The calibration block contains two parts CALIBRATION and LOAD CALIBRATION if thecalibration block configure as CALIBRATION then this register represent the result of calibration when calibration is completed if configure as LOAD CALIBRATION configure this register before loading calibration action, after loading calibration complete, the loaded calibration word will apply to the ADC while in loading calibration function the loaded value will not be equal to the original CALWORD until calibration is done.
bits : 0 - 6 (7 bit)
access : read-write

EXTSMPT_CH0 : Additional ADC Sample Clockfor Channel 0\nIf the ADC input is unstable, user can set this register to increase the sampling time to get a stable ADC input signal. The default sampling time is 1 ADC clocks. The additional clock number will be inserted to lengthen the sampling clock.
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EXTSMPT_CH1 : Additional ADC Sample Clockfor Channel 1\nThe same as channel 0 description.
bits : 4 - 7 (4 bit)
access : read-write

EXTSMPT_CH2 : Additional ADC Sample Clockfor Channel 2\nThe same as channel 0 description.
bits : 8 - 11 (4 bit)
access : read-write

EXTSMPT_CH3 : Additional ADC Sample Clockfor Channel 3\nThe same as channel 0 description.
bits : 12 - 15 (4 bit)
access : read-write

EXTSMPT_CH4 : Additional ADC Sample Clockfor Channel 4\nThe same as channel 0 description.
bits : 16 - 19 (4 bit)
access : read-write

EXTSMPT_CH5 : Additional ADC Sample Clockfor Channel 5\nThe same as channel 0 description.
bits : 20 - 23 (4 bit)
access : read-write

EXTSMPT_CH6 : Additional ADC Sample Clockfor Channel 6\nThe same as channel 0 description.
bits : 24 - 27 (4 bit)
access : read-write

EXTSMPT_CH7 : Additional ADC Sample Clockfor Channel 7\nThe same as channel 0 description.
bits : 28 - 31 (4 bit)
access : read-write

EXTSMPT_INTCH : Additional ADC Sample Clock for Internal Channel (VTEMP, AVDD, AVSS, Int_VREF, VBAT, VBG)\nThe same as channel 0 description.
bits : 16 - 19 (4 bit)
access : read-write