UUART_CTL

UUART_DATIN0

UUART_CTLIN0

UUART_CLKIN

UUART_LINECTL

UUART_TXDAT

UUART_RXDAT

UUART_BUFCTL

UUART_BUFSTS

UUART_INTEN

UUART_WKCTL

UUART_WKSTS

UUART_PROTCTL

UUART_PROTIEN

UUART_PROTSTS

UUART_BRGEN

FUNMODE : Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

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SYNCSEL : Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
bits : 0 - 0 (1 bit)
access : read-write

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ININV : Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.
bits : 2 - 2 (1 bit)
access : read-write

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EDGEDET : Input Signal Edge Detection Mode\nThis bit field selects which edge actives the trigger event of input data signal.\nNote: In UART function mode, it is suggested to set this bit field as 10.
bits : 3 - 4 (2 bit)
access : read-write

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SYNCSEL : Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
bits : 0 - 0 (1 bit)
access : read-write

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ININV : Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.
bits : 2 - 2 (1 bit)
access : read-write

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SYNCSEL : Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
bits : 0 - 0 (1 bit)
access : read-write

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LSB : LSB First Transmission Selection
bits : 0 - 0 (1 bit)
access : read-write

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DATOINV : Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin.
bits : 5 - 5 (1 bit)
access : read-write

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CTLOINV : Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: In UART protocol, the control signal means nRTS signal.
bits : 7 - 7 (1 bit)
access : read-write

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DWIDTH : Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0].\nNote: In UART protocol, the length can be configured as 6~13 bits.
bits : 8 - 11 (4 bit)
access : read-write

TXDAT : Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission.
bits : 0 - 15 (16 bit)
access : write-only

RXDAT : Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UUART_PROTSTS[7:5]).
bits : 0 - 15 (16 bit)
access : read-only

TXCLR : Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle.
bits : 7 - 7 (1 bit)
access : read-write

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RXOVIEN : Receive Buffer Overrun Error Interrupt Enable Bit
bits : 14 - 14 (1 bit)
access : read-write

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RXCLR : Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle.
bits : 15 - 15 (1 bit)
access : read-write

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TXRST : Transmit Reset\nNote: It is cleared automatically after one PCLK cycle.
bits : 16 - 16 (1 bit)
access : read-write

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RXRST : Receive Reset\nNote 1: It is cleared automatically after one PCLK cycle.\nNote 2: It is suggest to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1.
bits : 17 - 17 (1 bit)
access : read-write

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RXFULL : Receive Buffer Full Indicator
bits : 1 - 1 (1 bit)
access : read-only

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RXOVIF : Receive Buffer Over-run Error Interrupt Status\nThis bit indicates that a receive buffer overrun error event has been detected. If RXOVIEN (UUART_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit.
bits : 3 - 3 (1 bit)
access : read-only

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TXEMPTY : Transmit Buffer Empty Indicator
bits : 8 - 8 (1 bit)
access : read-only

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TXFULL : Transmit Buffer Full Indicator
bits : 9 - 9 (1 bit)
access : read-only

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TXSTIEN : Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event.
bits : 1 - 1 (1 bit)
access : read-write

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TXENDIEN : Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event.
bits : 2 - 2 (1 bit)
access : read-write

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RXSTIEN : Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event.
bits : 3 - 3 (1 bit)
access : read-write

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RXENDIEN : Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event.
bits : 4 - 4 (1 bit)
access : read-write

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WKEN : Wake-up Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

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PDBOPT : Power Down Blocking Option
bits : 2 - 2 (1 bit)
access : read-write

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WKF : Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

STOPB : Stop Bits\nThis bit defines the number of stop bits in an UART frame.
bits : 0 - 0 (1 bit)
access : read-write

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PARITYEN : Parity Enable Bit\nThis bit defines the parity bit is enabled in an UART frame.
bits : 1 - 1 (1 bit)
access : read-write

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EVENPARITY : Even Parity Enable Bit\nNote: This bit has effect only when PARITYEN is set.
bits : 2 - 2 (1 bit)
access : read-write

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ABREN : Auto-baud Rate Detect Enable Bit\nNote: When the auto - baud rate detect operation finishes, hardware will clear this bit. The associated interrupt ABRDETIF (USCI_PROTST[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled).
bits : 6 - 6 (1 bit)
access : read-write

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LINBRKEN : LIN TX Break Mode Enable Bit\nNote1: When TX break field transfer operation is finished, this bit will be cleared automatically.\nNote2: 13-bit level 0 and 1-bit level 1 were sent out before the 1st data be transmitted.
bits : 7 - 7 (1 bit)
access : read-write

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LINRXEN : LIN RX Duplex Mode Enable Bit\nNote: This bit is used to check the break duration for incoming data when the LIN operation is active.
bits : 8 - 8 (1 bit)
access : read-write

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DATWKEN : Data Wake-up Mode Enable Bit
bits : 9 - 9 (1 bit)
access : read-write

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WAKECNT : Wake-up Counter\nThese bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is woken up from Power-down mode.
bits : 11 - 14 (4 bit)
access : read-write

BRDETITV : Baud Rate Detection Interval \nThis bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits. The order of the bus shall be 1 and 0 step by step (e.g. the input data pattern shall be 0x55). The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (UUART_PROTCTL[9]) is set.\nNote: This bit can be cleared to 0 by software writing '0' to the BRDETITV.
bits : 16 - 24 (9 bit)
access : read-write

STICKEN : Stick Parity Enable Bit
bits : 26 - 26 (1 bit)
access : read-write

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BCEN : Transmit Break Control Enable Bit\nNote: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
bits : 29 - 29 (1 bit)
access : read-write

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PROTEN : UART Protocol Enable Bit
bits : 31 - 31 (1 bit)
access : read-write

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BRKIEN : LIN Break Detected Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

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ABRIEN : Auto-baud Rate Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

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RLSIEN : Receive Line Status Interrupt Enable Bit\nNote: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt.
bits : 2 - 2 (1 bit)
access : read-write

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TXSTIF : Transmit Start Interrupt Flag\nNote 1: It is cleared by software writing one into this bit.\nNote 2: Used for user to load next transmit data when there is no data in transmit buffer.
bits : 1 - 1 (1 bit)
access : read-write

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TXENDIF : Transmit End Interrupt Flag\nNote: It is cleared by software writing one into this bit.
bits : 2 - 2 (1 bit)
access : read-write

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RXSTIF : Receive Start Interrupt Flag\nNote: It is cleared by software writing one into this bit.
bits : 3 - 3 (1 bit)
access : read-write

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RXENDIF : Receive End Interrupt Flag\nNote: It is cleared by software writing one into this bit.
bits : 4 - 4 (1 bit)
access : read-write

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PARITYERR : Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits.
bits : 5 - 5 (1 bit)
access : read-write

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FRMERR : Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits.
bits : 6 - 6 (1 bit)
access : read-write

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BREAK : Break Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).\nNote: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits.
bits : 7 - 7 (1 bit)
access : read-write

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BRKDETIF : LIN Break Detected Interrupt Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than 12-bit transmission time in LIN mode function.\nNote: This bit is read only, but can be cleared by writing '1' to it.
bits : 8 - 8 (1 bit)
access : read-only

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ABRDETIF : Auto-baud Rate Interrupt Flag This bit is set when auto-baud rate detection is done among the falling edge of the input data. If the ABRIEN (UUART_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated. This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus. Note: This bit can be cleared by writing '1' to it.
bits : 9 - 9 (1 bit)
access : read-write

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RXBUSY : RX Bus Status Flag (Read Only) \nThis bit indicates the busy status of the receiver.
bits : 10 - 10 (1 bit)
access : read-only

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ABERRSTS : Auto-baud Rate Error Status \nThis bit is set when auto-baud rate detection counter overrun. When the auto-baud rate counter overrun, the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the correct baud rate again.\nNote 1: This bit is set at the same time of ABRDETIF.\nNote 2: This bit can be cleared by writing '1' to ABRDETIF or ABERRSTS.
bits : 11 - 11 (1 bit)
access : read-write

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RCLKSEL : Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK).
bits : 0 - 0 (1 bit)
access : read-write

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PTCLKSEL : Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK).
bits : 1 - 1 (1 bit)
access : read-write

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SPCLKSEL : Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
bits : 2 - 3 (2 bit)
access : read-write

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TMCNTEN : Timing Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter.
bits : 4 - 4 (1 bit)
access : read-write

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TMCNTSRC : Timing Measurement Counter Clock Source Selection
bits : 5 - 5 (1 bit)
access : read-write

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PDSCNT : Pre-divider for Sample Counter
bits : 8 - 9 (2 bit)
access : read-write

DSCNT : Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value.
bits : 10 - 14 (5 bit)
access : read-write

CLKDIV : Clock Divider\nNote: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and bit 6. The user can use revised CLKDIV and new BRDETITV (UUART_PROTCTL[24:16]) to calculate the precise baud rate.
bits : 16 - 25 (10 bit)
access : read-write