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DSI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x800 byte (0x0)
mem_usage : registers
protection : not protected

Registers

DSI_VR (VR)

DSI_LCOLCR (LCOLCR)

DSI_VSCR (VSCR)

DSI_LCVCIDR (LCVCIDR)

DSI_LCCCR (LCCCR)

DSI_LPMCCR (LPMCCR)

DSI_VMCCR (VMCCR)

DSI_VPCCR (VPCCR)

DSI_LPCR (LPCR)

DSI_VCCCR (VCCCR)

DSI_VNPCCR (VNPCCR)

DSI_VHSACCR (VHSACCR)

DSI_VHBPCCR (VHBPCCR)

DSI_VLCCR (VLCCR)

DSI_VVSACCR (VVSACCR)

DSI_VVBPCCR (VVBPCCR)

DSI_VVFPCCR (VVFPCCR)

DSI_VVACCR (VVACCR)

DSI_LPMCR (LPMCR)

DSI_PCR (PCR)

DSI_GVCIDR (GVCIDR)

DSI_MCR (MCR)

DSI_VMCR (VMCR)

DSI_VPCR (VPCR)

DSI_CR (CR)

DSI_VCCR (VCCR)

DSI_WCFGR (WCFGR)

DSI_WCR (WCR)

DSI_WIER (WIER)

DSI_WISR (WISR)

DSI_WIFCR (WIFCR)

DSI_WPCR0 (WPCR0)

DSI_WPCR1 (WPCR1)

DSI_WPCR2 (WPCR2)

DSI_WPCR3 (WPCR3)

DSI_WPCR4 (WPCR4)

DSI_WPCR5 (WPCR5)

DSI_WRPCR (WRPCR)

DSI_VNPCR (VNPCR)

DSI_VHSACR (VHSACR)

DSI_VHBPCR (VHBPCR)

DSI_VLCR (VLCR)

DSI_VVSACR (VVSACR)

DSI_VVBPCR (VVBPCR)

DSI_VVFPCR (VVFPCR)

DSI_VVACR (VVACR)

DSI_LCCR (LCCR)

DSI_CMCR (CMCR)

DSI_GHCR (GHCR)

DSI_GPDR (GPDR)

DSI_GPSR (GPSR)

DSI_TCCR0 (TCCR0)

DSI_TCCR1 (TCCR1)

DSI_CCR (CCR)

DSI_TCCR2 (TCCR2)

DSI_TCCR3 (TCCR3)

DSI_TCCR4 (TCCR4)

DSI_TCCR5 (TCCR5)

DSI_CLCR (CLCR)

DSI_CLTCR (CLTCR)

DSI_DLTRC (DLTRC)

DSI_PCTLR (PCTLR)

DSI_PCONFR (PCONFR)

DSI_PUCR (PUCR)

DSI_PTTCR (PTTCR)

DSI_PSR (PSR)

DSI_ISR0 (ISR0)

DSI_LVCIDR (LVCIDR)

DSI_ISR1 (ISR1)

DSI_IER0 (IER0)

DSI_IER1 (IER1)

DSI_FIR0 (FIR0)

DSI_FIR1 (FIR1)


DSI_VR (VR)

DSI Host Version Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VR DSI_VR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION

VERSION : Version of the DSI Host
bits : 0 - 31 (32 bit)


DSI_LCOLCR (LCOLCR)

DSI Host LTDC Color Coding Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_LCOLCR DSI_LCOLCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COLC LPE

COLC : Color Coding
bits : 0 - 3 (4 bit)

LPE : Loosely Packet Enable
bits : 8 - 8 (1 bit)


DSI_VSCR (VSCR)

DSI Host Video Shadow Control Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VSCR DSI_VSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN UR

EN : Enable
bits : 0 - 0 (1 bit)

UR : Update Register
bits : 8 - 8 (1 bit)


DSI_LCVCIDR (LCVCIDR)

DSI Host LTDC Current VCID Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_LCVCIDR DSI_LCVCIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCID

VCID : Virtual Channel ID
bits : 0 - 1 (2 bit)


DSI_LCCCR (LCCCR)

DSI Host LTDC Current Color Coding Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_LCCCR DSI_LCCCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COLC LPE

COLC : Color Coding
bits : 0 - 3 (4 bit)

LPE : Loosely Packed Enable
bits : 8 - 8 (1 bit)


DSI_LPMCCR (LPMCCR)

DSI Host Low-Power mode Current Configuration Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_LPMCCR DSI_LPMCCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VLPSIZE LPSIZE

VLPSIZE : VACT Largest Packet Size
bits : 0 - 7 (8 bit)

LPSIZE : Largest Packet Size
bits : 16 - 23 (8 bit)


DSI_VMCCR (VMCCR)

DSI Host Video mode Current Configuration Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VMCCR DSI_VMCCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VMT LPVSAE LPVBPE LPVFPE LPVAE LPHBPE LPHFE FBTAAE LPCE

VMT : Video mode Type
bits : 0 - 1 (2 bit)

LPVSAE : Low-Power Vertical Sync time Enable
bits : 2 - 2 (1 bit)

LPVBPE : Low-power Vertical Back-Porch Enable
bits : 3 - 3 (1 bit)

LPVFPE : Low-power Vertical Front-Porch Enable
bits : 4 - 4 (1 bit)

LPVAE : Low-Power Vertical Active Enable
bits : 5 - 5 (1 bit)

LPHBPE : Low-power Horizontal Back-Porch Enable
bits : 6 - 6 (1 bit)

LPHFE : Low-Power Horizontal Front-Porch Enable
bits : 7 - 7 (1 bit)

FBTAAE : Frame BTA Acknowledge Enable
bits : 8 - 8 (1 bit)

LPCE : Low-Power Command Enable
bits : 9 - 9 (1 bit)


DSI_VPCCR (VPCCR)

DSI Host Video Packet Current Configuration Register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VPCCR DSI_VPCCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VPSIZE

VPSIZE : Video Packet Size
bits : 0 - 13 (14 bit)


DSI_LPCR (LPCR)

DSI Host LTDC Polarity Configuration Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_LPCR DSI_LPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEP VSP HSP

DEP : Data Enable Polarity
bits : 0 - 0 (1 bit)

VSP : VSYNC Polarity
bits : 1 - 1 (1 bit)

HSP : HSYNC Polarity
bits : 2 - 2 (1 bit)


DSI_VCCCR (VCCCR)

DSI Host Video Chunks Current Configuration Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VCCCR DSI_VCCCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NUMC

NUMC : Number of Chunks
bits : 0 - 12 (13 bit)


DSI_VNPCCR (VNPCCR)

DSI Host Video Null Packet Current Configuration Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VNPCCR DSI_VNPCCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NPSIZE

NPSIZE : Null Packet Size
bits : 0 - 12 (13 bit)


DSI_VHSACCR (VHSACCR)

DSI Host Video HSA Current Configuration Register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VHSACCR DSI_VHSACCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSA

HSA : Horizontal Synchronism Active duration
bits : 0 - 11 (12 bit)


DSI_VHBPCCR (VHBPCCR)

DSI Host Video HBP Current Configuration Register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VHBPCCR DSI_VHBPCCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HBP

HBP : Horizontal Back-Porch duration
bits : 0 - 11 (12 bit)


DSI_VLCCR (VLCCR)

DSI Host Video Line Current Configuration Register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VLCCR DSI_VLCCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HLINE

HLINE : Horizontal Line duration
bits : 0 - 14 (15 bit)


DSI_VVSACCR (VVSACCR)

DSI Host Video VSA Current Configuration Register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VVSACCR DSI_VVSACCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSA

VSA : Vertical Synchronism Active duration
bits : 0 - 9 (10 bit)


DSI_VVBPCCR (VVBPCCR)

DSI Host Video VBP Current Configuration Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VVBPCCR DSI_VVBPCCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VBP

VBP : Vertical Back-Porch duration
bits : 0 - 9 (10 bit)


DSI_VVFPCCR (VVFPCCR)

DSI Host Video VFP Current Configuration Register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VVFPCCR DSI_VVFPCCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VFP

VFP : Vertical Front-Porch duration
bits : 0 - 9 (10 bit)


DSI_VVACCR (VVACCR)

DSI Host Video VA Current Configuration Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_VVACCR DSI_VVACCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VA

VA : Vertical Active duration
bits : 0 - 13 (14 bit)


DSI_LPMCR (LPMCR)

DSI Host Low-Power mode Configuration Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_LPMCR DSI_LPMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VLPSIZE LPSIZE

VLPSIZE : VACT Largest Packet Size
bits : 0 - 7 (8 bit)

LPSIZE : Largest Packet Size
bits : 16 - 23 (8 bit)


DSI_PCR (PCR)

DSI Host Protocol Configuration Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_PCR DSI_PCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETTXE ETRXE BTAE ECCRXE CRCRXE

ETTXE : EoTp Transmission Enable
bits : 0 - 0 (1 bit)

ETRXE : EoTp Reception Enable
bits : 1 - 1 (1 bit)

BTAE : Bus Turn Around Enable
bits : 2 - 2 (1 bit)

ECCRXE : ECC Reception Enable
bits : 3 - 3 (1 bit)

CRCRXE : CRC Reception Enable
bits : 4 - 4 (1 bit)


DSI_GVCIDR (GVCIDR)

DSI Host Generic VCID Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_GVCIDR DSI_GVCIDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCID

VCID : Virtual Channel ID
bits : 0 - 1 (2 bit)


DSI_MCR (MCR)

DSI Host mode Configuration Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_MCR DSI_MCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDM

CMDM : Command mode
bits : 0 - 0 (1 bit)


DSI_VMCR (VMCR)

DSI Host Video mode Configuration Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VMCR DSI_VMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VMT LPVSAE LPVBPE LPVFPE LPVAE LPHBPE LPHFPE FBTAAE LPCE PGE PGM PGO

VMT : Video mode Type
bits : 0 - 1 (2 bit)

LPVSAE : Low-Power Vertical Sync Active Enable
bits : 8 - 8 (1 bit)

LPVBPE : Low-power Vertical Back-Porch Enable
bits : 9 - 9 (1 bit)

LPVFPE : Low-power Vertical Front-porch Enable
bits : 10 - 10 (1 bit)

LPVAE : Low-Power Vertical Active Enable
bits : 11 - 11 (1 bit)

LPHBPE : Low-Power Horizontal Back-Porch Enable
bits : 12 - 12 (1 bit)

LPHFPE : Low-Power Horizontal Front-Porch Enable
bits : 13 - 13 (1 bit)

FBTAAE : Frame Bus-Turn-Around Acknowledge Enable
bits : 14 - 14 (1 bit)

LPCE : Low-Power Command Enable
bits : 15 - 15 (1 bit)

PGE : Pattern Generator Enable
bits : 16 - 16 (1 bit)

PGM : Pattern Generator mode
bits : 20 - 20 (1 bit)

PGO : Pattern Generator Orientation
bits : 24 - 24 (1 bit)


DSI_VPCR (VPCR)

DSI Host Video Packet Configuration Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VPCR DSI_VPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VPSIZE

VPSIZE : Video Packet Size
bits : 0 - 13 (14 bit)


DSI_CR (CR)

DSI Host Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_CR DSI_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN

EN : Enable
bits : 0 - 0 (1 bit)


DSI_VCCR (VCCR)

DSI Host Video Chunks Configuration Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VCCR DSI_VCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NUMC

NUMC : Number of Chunks
bits : 0 - 12 (13 bit)


DSI_WCFGR (WCFGR)

DSI Wrapper Configuration Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_WCFGR DSI_WCFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSIM COLMUX TESRC TEPOL AR VSPOL

DSIM : DSI Mode
bits : 0 - 0 (1 bit)

COLMUX : Color Multiplexing
bits : 1 - 3 (3 bit)

TESRC : TE Source
bits : 4 - 4 (1 bit)

TEPOL : TE Polarity
bits : 5 - 5 (1 bit)

AR : Automatic Refresh
bits : 6 - 6 (1 bit)

VSPOL : VSync Polarity
bits : 7 - 7 (1 bit)


DSI_WCR (WCR)

DSI Wrapper Control Register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_WCR DSI_WCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COLM SHTDN LTDCEN DSIEN

COLM : Color Mode
bits : 0 - 0 (1 bit)

SHTDN : Shutdown
bits : 1 - 1 (1 bit)

LTDCEN : LTDC Enable
bits : 2 - 2 (1 bit)

DSIEN : DSI Enable
bits : 3 - 3 (1 bit)


DSI_WIER (WIER)

DSI Wrapper Interrupt Enable Register
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_WIER DSI_WIER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEIE ERIE PLLLIE PLLUIE RRIE

TEIE : Tearing Effect Interrupt Enable
bits : 0 - 0 (1 bit)

ERIE : End of Refresh Interrupt Enable
bits : 1 - 1 (1 bit)

PLLLIE : PLL Lock Interrupt Enable
bits : 9 - 9 (1 bit)

PLLUIE : PLL Unlock Interrupt Enable
bits : 10 - 10 (1 bit)

RRIE : Regulator Ready Interrupt Enable
bits : 13 - 13 (1 bit)


DSI_WISR (WISR)

DSI Wrapper Interrupt and Status Register
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_WISR DSI_WISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEIF ERIF BUSY PLLLS PLLLIF PLLUIF RRS RRIF

TEIF : Tearing Effect Interrupt Flag
bits : 0 - 0 (1 bit)

ERIF : End of Refresh Interrupt Flag
bits : 1 - 1 (1 bit)

BUSY : Busy Flag
bits : 2 - 2 (1 bit)

PLLLS : PLL Lock Status
bits : 8 - 8 (1 bit)

PLLLIF : PLL Lock Interrupt Flag
bits : 9 - 9 (1 bit)

PLLUIF : PLL Unlock Interrupt Flag
bits : 10 - 10 (1 bit)

RRS : Regulator Ready Status
bits : 12 - 12 (1 bit)

RRIF : Regulator Ready Interrupt Flag
bits : 13 - 13 (1 bit)


DSI_WIFCR (WIFCR)

DSI Wrapper Interrupt Flag Clear Register
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_WIFCR DSI_WIFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTEIF CERIF CPLLLIF CPLLUIF CRRIF

CTEIF : Clear Tearing Effect Interrupt Flag
bits : 0 - 0 (1 bit)

CERIF : Clear End of Refresh Interrupt Flag
bits : 1 - 1 (1 bit)

CPLLLIF : Clear PLL Lock Interrupt Flag
bits : 9 - 9 (1 bit)

CPLLUIF : Clear PLL Unlock Interrupt Flag
bits : 10 - 10 (1 bit)

CRRIF : Clear Regulator Ready Interrupt Flag
bits : 13 - 13 (1 bit)


DSI_WPCR0 (WPCR0)

DSI Wrapper PHY Configuration Register 0
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_WPCR0 DSI_WPCR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UIX4 SWCL SWDL0 SWDL1 HSICL HSIDL0 HSIDL1 FTXSMCL FTXSMDL CDOFFDL TDDL PDEN TCLKPREPEN TCLKZEROEN THSPREPEN THSTRAILEN THSZEROEN TLPXDEN THSEXITEN TLPXCEN TCLKPOSTEN

UIX4 : Unit Interval multiplied by 4
bits : 0 - 5 (6 bit)

SWCL : Swap Clock Lane pins
bits : 6 - 6 (1 bit)

SWDL0 : Swap Data Lane 0 pins
bits : 7 - 7 (1 bit)

SWDL1 : Swap Data Lane 1 pins
bits : 8 - 8 (1 bit)

HSICL : Invert Hight-Speed data signal on Clock Lane
bits : 9 - 9 (1 bit)

HSIDL0 : Invert the Hight-Speed data signal on Data Lane 0
bits : 10 - 10 (1 bit)

HSIDL1 : Invert the High-Speed data signal on Data Lane 1
bits : 11 - 11 (1 bit)

FTXSMCL : Force in TX Stop Mode the Clock Lane
bits : 12 - 12 (1 bit)

FTXSMDL : Force in TX Stop Mode the Data Lanes
bits : 13 - 13 (1 bit)

CDOFFDL : Contention Detection OFF on Data Lanes
bits : 14 - 14 (1 bit)

TDDL : Turn Disable Data Lanes
bits : 16 - 16 (1 bit)

PDEN : Pull-Down Enable
bits : 18 - 18 (1 bit)

TCLKPREPEN : custom time for tCLK-PREPARE Enable
bits : 19 - 19 (1 bit)

TCLKZEROEN : custom time for tCLK-ZERO Enable
bits : 20 - 20 (1 bit)

THSPREPEN : custom time for tHS-PREPARE Enable
bits : 21 - 21 (1 bit)

THSTRAILEN : custom time for tHS-TRAIL Enable
bits : 22 - 22 (1 bit)

THSZEROEN : custom time for tHS-ZERO Enable
bits : 23 - 23 (1 bit)

TLPXDEN : custom time for tLPX for Data lanes Enable
bits : 24 - 24 (1 bit)

THSEXITEN : custom time for tHS-EXIT Enable
bits : 25 - 25 (1 bit)

TLPXCEN : custom time for tLPX for Clock lane Enable
bits : 26 - 26 (1 bit)

TCLKPOSTEN : custom time for tCLK-POST Enable
bits : 27 - 27 (1 bit)


DSI_WPCR1 (WPCR1)

DSI Wrapper PHY Configuration Register 1
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_WPCR1 DSI_WPCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UIX4 HSTXDCL HSTXDLL SWCL LPSRCL SWDL0 SWDL1 LPSRDL HSICL HSIDL0 HSIDL1 FTXSMCL SDCC FTXSMDL CDOFFDL TDDL HSTXSRCCL PDEN HSTXSRCDL TCLKPREPEN TCLKZEROEN THSPREPEN THSTRAILEN FLPRXLPM THSZEROEN TLPXDEN THSEXITEN LPRXFT TLPXCEN TCLKPOSTEN

UIX4 : Unit Interval multiplied by 4
bits : 0 - 5 (6 bit)

HSTXDCL : High-Speed Transmission Delay on Clock Lane
bits : 0 - 1 (2 bit)

HSTXDLL : High-Speed Transmission Delay on Data Lanes
bits : 2 - 3 (2 bit)

SWCL : Swap Clock Lane pins
bits : 6 - 6 (1 bit)

LPSRCL : Low-Power transmission Slew Rate Compensation on Clock Lane
bits : 6 - 7 (2 bit)

SWDL0 : Swap Data Lane 0 pins
bits : 7 - 7 (1 bit)

SWDL1 : Swap Data Lane 1 pins
bits : 8 - 8 (1 bit)

LPSRDL : Low-Power transmission Slew Rate Compensation on Data Lanes
bits : 8 - 9 (2 bit)

HSICL : Invert Hight-Speed data signal on Clock Lane
bits : 9 - 9 (1 bit)

HSIDL0 : Invert the Hight-Speed data signal on Data Lane 0
bits : 10 - 10 (1 bit)

HSIDL1 : Invert the High-Speed data signal on Data Lane 1
bits : 11 - 11 (1 bit)

FTXSMCL : Force in TX Stop Mode the Clock Lane
bits : 12 - 12 (1 bit)

SDCC : SDD Control
bits : 12 - 12 (1 bit)

FTXSMDL : Force in TX Stop Mode the Data Lanes
bits : 13 - 13 (1 bit)

CDOFFDL : Contention Detection OFF on Data Lanes
bits : 14 - 14 (1 bit)

TDDL : Turn Disable Data Lanes
bits : 16 - 16 (1 bit)

HSTXSRCCL : High-Speed Transmission Slew Rate Control on Clock Lane
bits : 16 - 17 (2 bit)

PDEN : Pull-Down Enable
bits : 18 - 18 (1 bit)

HSTXSRCDL : High-Speed Transmission Slew Rate Control on Data Lanes
bits : 18 - 19 (2 bit)

TCLKPREPEN : custom time for tCLK-PREPARE Enable
bits : 19 - 19 (1 bit)

TCLKZEROEN : custom time for tCLK-ZERO Enable
bits : 20 - 20 (1 bit)

THSPREPEN : custom time for tHS-PREPARE Enable
bits : 21 - 21 (1 bit)

THSTRAILEN : custom time for tHS-TRAIL Enable
bits : 22 - 22 (1 bit)

FLPRXLPM : Forces LP Receiver in Low-Power Mode
bits : 22 - 22 (1 bit)

THSZEROEN : custom time for tHS-ZERO Enable
bits : 23 - 23 (1 bit)

TLPXDEN : custom time for tLPX for Data lanes Enable
bits : 24 - 24 (1 bit)

THSEXITEN : custom time for tHS-EXIT Enable
bits : 25 - 25 (1 bit)

LPRXFT : Low-Power RX low-pass Filtering Tuning
bits : 25 - 26 (2 bit)

TLPXCEN : custom time for tLPX for Clock lane Enable
bits : 26 - 26 (1 bit)

TCLKPOSTEN : custom time for tCLK-POST Enable
bits : 27 - 27 (1 bit)


DSI_WPCR2 (WPCR2)

DSI Wrapper PHY Configuration Register 2
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_WPCR2 DSI_WPCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSTXDCL TCLKPREP HSTXDLL LPSRCL LPSRDL TCLKZEO SDCC HSTXSRCCL THSPREP HSTXSRCDL FLPRXLPM THSTRAIL LPRXFT

HSTXDCL : High-Speed Transmission Delay on Clock Lane
bits : 0 - 1 (2 bit)

TCLKPREP : tCLK-PREPARE
bits : 0 - 7 (8 bit)

HSTXDLL : High-Speed Transmission Delay on Data Lanes
bits : 2 - 3 (2 bit)

LPSRCL : Low-Power transmission Slew Rate Compensation on Clock Lane
bits : 6 - 7 (2 bit)

LPSRDL : Low-Power transmission Slew Rate Compensation on Data Lanes
bits : 8 - 9 (2 bit)

TCLKZEO : tCLK-ZERO
bits : 8 - 15 (8 bit)

SDCC : SDD Control
bits : 12 - 12 (1 bit)

HSTXSRCCL : High-Speed Transmission Slew Rate Control on Clock Lane
bits : 16 - 17 (2 bit)

THSPREP : tHS-PREPARE
bits : 16 - 23 (8 bit)

HSTXSRCDL : High-Speed Transmission Slew Rate Control on Data Lanes
bits : 18 - 19 (2 bit)

FLPRXLPM : Forces LP Receiver in Low-Power Mode
bits : 22 - 22 (1 bit)

THSTRAIL : tHSTRAIL
bits : 24 - 31 (8 bit)

LPRXFT : Low-Power RX low-pass Filtering Tuning
bits : 25 - 26 (2 bit)


DSI_WPCR3 (WPCR3)

DSI_WPCR3
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_WPCR3 DSI_WPCR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCLKPREP THSZERO TCLKZEO TLPXD THSPREP THSEXIT THSTRAIL TLPXC

TCLKPREP : tCLK-PREPARE
bits : 0 - 7 (8 bit)

THSZERO : tHS-ZERO
bits : 0 - 7 (8 bit)

TCLKZEO : tCLK-ZERO
bits : 8 - 15 (8 bit)

TLPXD : tLPX for Data lanes
bits : 8 - 15 (8 bit)

THSPREP : tHS-PREPARE
bits : 16 - 23 (8 bit)

THSEXIT : tHSEXIT
bits : 16 - 23 (8 bit)

THSTRAIL : tHSTRAIL
bits : 24 - 31 (8 bit)

TLPXC : tLPXC for Clock lane
bits : 24 - 31 (8 bit)


DSI_WPCR4 (WPCR4)

DSI Wrapper PHY Configuration Register 4
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_WPCR4 DSI_WPCR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 THSZERO TLPXD THSEXIT TLPXC

THSZERO : tCLK-POST
bits : 0 - 7 (8 bit)

TLPXD : tLPX for Data lanes
bits : 8 - 15 (8 bit)

THSEXIT : tHSEXIT
bits : 16 - 23 (8 bit)

TLPXC : tLPXC for Clock lane
bits : 24 - 31 (8 bit)


DSI_WPCR5 (WPCR5)

DSI Wrapper PHY Configuration Register 5
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_WPCR5 DSI_WPCR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 THSZERO

THSZERO : tCLK-POST
bits : 0 - 7 (8 bit)


DSI_WRPCR (WRPCR)

DSI Wrapper Regulator and PLL Control Register
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_WRPCR DSI_WRPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLLEN NDIV IDF ODF REGEN

PLLEN : PLL Enable
bits : 0 - 0 (1 bit)

NDIV : PLL Loop Division Factor
bits : 2 - 8 (7 bit)

IDF : PLL Input Division Factor
bits : 11 - 14 (4 bit)

ODF : PLL Output Division Factor
bits : 16 - 17 (2 bit)

REGEN : Regulator Enable
bits : 24 - 24 (1 bit)


DSI_VNPCR (VNPCR)

DSI Host Video Null Packet Configuration Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VNPCR DSI_VNPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NPSIZE

NPSIZE : Null Packet Size
bits : 0 - 12 (13 bit)


DSI_VHSACR (VHSACR)

DSI Host Video HSA Configuration Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VHSACR DSI_VHSACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSA

HSA : Horizontal Synchronism Active duration
bits : 0 - 11 (12 bit)


DSI_VHBPCR (VHBPCR)

DSI Host Video HBP Configuration Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VHBPCR DSI_VHBPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HBP

HBP : Horizontal Back-Porch duration
bits : 0 - 11 (12 bit)


DSI_VLCR (VLCR)

DSI Host Video Line Configuration Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VLCR DSI_VLCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HLINE

HLINE : Horizontal Line duration
bits : 0 - 14 (15 bit)


DSI_VVSACR (VVSACR)

DSI Host Video VSA Configuration Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VVSACR DSI_VVSACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSA

VSA : Vertical Synchronism Active duration
bits : 0 - 9 (10 bit)


DSI_VVBPCR (VVBPCR)

DSI Host Video VBP Configuration Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VVBPCR DSI_VVBPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VBP

VBP : Vertical Back-Porch duration
bits : 0 - 9 (10 bit)


DSI_VVFPCR (VVFPCR)

DSI Host Video VFP Configuration Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VVFPCR DSI_VVFPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VFP

VFP : Vertical Front-Porch duration
bits : 0 - 9 (10 bit)


DSI_VVACR (VVACR)

DSI Host Video VA Configuration Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_VVACR DSI_VVACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VA

VA : Vertical Active duration
bits : 0 - 13 (14 bit)


DSI_LCCR (LCCR)

DSI Host LTDC Command Configuration Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_LCCR DSI_LCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDSIZE

CMDSIZE : Command Size
bits : 0 - 15 (16 bit)


DSI_CMCR (CMCR)

DSI Host Command mode Configuration Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_CMCR DSI_CMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEARE ARE GSW0TX GSW1TX GSW2TX GSR0TX GSR1TX GSR2TX GLWTX DSW0TX DSW1TX DSR0TX DLWTX MRDPS

TEARE : Tearing Effect Acknowledge Request Enable
bits : 0 - 0 (1 bit)

ARE : Acknowledge Request Enable
bits : 1 - 1 (1 bit)

GSW0TX : Generic Short Write Zero parameters Transmission
bits : 8 - 8 (1 bit)

GSW1TX : Generic Short Write One parameters Transmission
bits : 9 - 9 (1 bit)

GSW2TX : Generic Short Write Two parameters Transmission
bits : 10 - 10 (1 bit)

GSR0TX : Generic Short Read Zero parameters Transmission
bits : 11 - 11 (1 bit)

GSR1TX : Generic Short Read One parameters Transmission
bits : 12 - 12 (1 bit)

GSR2TX : Generic Short Read Two parameters Transmission
bits : 13 - 13 (1 bit)

GLWTX : Generic Long Write Transmission
bits : 14 - 14 (1 bit)

DSW0TX : DCS Short Write Zero parameter Transmission
bits : 16 - 16 (1 bit)

DSW1TX : DCS Short Read One parameter Transmission
bits : 17 - 17 (1 bit)

DSR0TX : DCS Short Read Zero parameter Transmission
bits : 18 - 18 (1 bit)

DLWTX : DCS Long Write Transmission
bits : 19 - 19 (1 bit)

MRDPS : Maximum Read Packet Size
bits : 24 - 24 (1 bit)


DSI_GHCR (GHCR)

DSI Host Generic Header Configuration Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_GHCR DSI_GHCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DT VCID WCLSB WCMSB

DT : Type
bits : 0 - 5 (6 bit)

VCID : Channel
bits : 6 - 7 (2 bit)

WCLSB : WordCount LSB
bits : 8 - 15 (8 bit)

WCMSB : WordCount MSB
bits : 16 - 23 (8 bit)


DSI_GPDR (GPDR)

DSI Host Generic Payload Data Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_GPDR DSI_GPDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA1 DATA2 DATA3 DATA4

DATA1 : Payload Byte 1
bits : 0 - 7 (8 bit)

DATA2 : Payload Byte 2
bits : 8 - 15 (8 bit)

DATA3 : Payload Byte 3
bits : 16 - 23 (8 bit)

DATA4 : Payload Byte 4
bits : 24 - 31 (8 bit)


DSI_GPSR (GPSR)

DSI Host Generic Packet Status Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_GPSR DSI_GPSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDFE CMDFF PWRFE PWRFF PRDFE PRDFF RCB

CMDFE : Command FIFO Empty
bits : 0 - 0 (1 bit)

CMDFF : Command FIFO Full
bits : 1 - 1 (1 bit)

PWRFE : Payload Write FIFO Empty
bits : 2 - 2 (1 bit)

PWRFF : Payload Write FIFO Full
bits : 3 - 3 (1 bit)

PRDFE : Payload Read FIFO Empty
bits : 4 - 4 (1 bit)

PRDFF : Payload Read FIFO Full
bits : 5 - 5 (1 bit)

RCB : Read Command Busy
bits : 6 - 6 (1 bit)


DSI_TCCR0 (TCCR0)

DSI Host Timeout Counter Configuration Register 0
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_TCCR0 DSI_TCCR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPRX_TOCNT HSTX_TOCNT

LPRX_TOCNT : Low-power Reception Timeout Counter
bits : 0 - 15 (16 bit)

HSTX_TOCNT : High-Speed Transmission Timeout Counter
bits : 16 - 31 (16 bit)


DSI_TCCR1 (TCCR1)

DSI Host Timeout Counter Configuration Register 1
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_TCCR1 DSI_TCCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSRD_TOCNT

HSRD_TOCNT : High-Speed Read Timeout Counter
bits : 0 - 15 (16 bit)


DSI_CCR (CCR)

DSI HOST Clock Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_CCR DSI_CCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXECKDIV TOCKDIV

TXECKDIV : TX Escape Clock Division
bits : 0 - 7 (8 bit)

TOCKDIV : Timeout Clock Division
bits : 8 - 15 (8 bit)


DSI_TCCR2 (TCCR2)

DSI Host Timeout Counter Configuration Register 2
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_TCCR2 DSI_TCCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPRD_TOCNT

LPRD_TOCNT : Low-Power Read Timeout Counter
bits : 0 - 15 (16 bit)


DSI_TCCR3 (TCCR3)

DSI Host Timeout Counter Configuration Register 3
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_TCCR3 DSI_TCCR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSWR_TOCNT PM

HSWR_TOCNT : High-Speed Write Timeout Counter
bits : 0 - 15 (16 bit)

PM : Presp mode
bits : 24 - 24 (1 bit)


DSI_TCCR4 (TCCR4)

DSI Host Timeout Counter Configuration Register 4
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_TCCR4 DSI_TCCR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSWR_TOCNT

LSWR_TOCNT : Low-Power Write Timeout Counter
bits : 0 - 15 (16 bit)


DSI_TCCR5 (TCCR5)

DSI Host Timeout Counter Configuration Register 5
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_TCCR5 DSI_TCCR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BTA_TOCNT

BTA_TOCNT : Bus-Turn-Around Timeout Counter
bits : 0 - 15 (16 bit)


DSI_CLCR (CLCR)

DSI Host Clock Lane Configuration Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_CLCR DSI_CLCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DPCC ACR

DPCC : D-PHY Clock Control
bits : 0 - 0 (1 bit)

ACR : Automatic Clock lane Control
bits : 1 - 1 (1 bit)


DSI_CLTCR (CLTCR)

DSI Host Clock Lane Timer Configuration Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_CLTCR DSI_CLTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LP2HS_TIME HS2LP_TIME

LP2HS_TIME : Low-Power to High-Speed Time
bits : 0 - 9 (10 bit)

HS2LP_TIME : High-Speed to Low-Power Time
bits : 16 - 25 (10 bit)


DSI_DLTRC (DLTRC)

DSI Host Data Lane Timer Configuration Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_DLTRC DSI_DLTRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MRD_TIME LP2HS_TIME HS2LP_TIME

MRD_TIME : Maximum Read Time
bits : 0 - 14 (15 bit)

LP2HS_TIME : Low-Power To High-Speed Time
bits : 16 - 23 (8 bit)

HS2LP_TIME : High-Speed To Low-Power Time
bits : 24 - 31 (8 bit)


DSI_PCTLR (PCTLR)

DSI Host PHY Control Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_PCTLR DSI_PCTLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEN CKE

DEN : Digital Enable
bits : 1 - 1 (1 bit)

CKE : Clock Enable
bits : 2 - 2 (1 bit)


DSI_PCONFR (PCONFR)

DSI Host PHY Configuration Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_PCONFR DSI_PCONFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NL SW_TIME

NL : Number of Lanes
bits : 0 - 1 (2 bit)

SW_TIME : Stop Wait Time
bits : 8 - 15 (8 bit)


DSI_PUCR (PUCR)

DSI Host PHY ULPS Control Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_PUCR DSI_PUCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 URCL UECL URDL UEDL

URCL : ULPS Request on Clock Lane
bits : 0 - 0 (1 bit)

UECL : ULPS Exit on Clock Lane
bits : 1 - 1 (1 bit)

URDL : ULPS Request on Data Lane
bits : 2 - 2 (1 bit)

UEDL : ULPS Exit on Data Lane
bits : 3 - 3 (1 bit)


DSI_PTTCR (PTTCR)

DSI Host PHY TX Triggers Configuration Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_PTTCR DSI_PTTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_TRIG

TX_TRIG : Transmission Trigger
bits : 0 - 3 (4 bit)


DSI_PSR (PSR)

DSI Host PHY Status Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_PSR DSI_PSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PD PSSC UANC PSS0 UAN0 RUE0 PSS1 UAN1

PD : PHY Direction
bits : 1 - 1 (1 bit)

PSSC : PHY Stop State Clock lane
bits : 2 - 2 (1 bit)

UANC : ULPS Active Not Clock lane
bits : 3 - 3 (1 bit)

PSS0 : PHY Stop State lane 0
bits : 4 - 4 (1 bit)

UAN0 : ULPS Active Not lane 1
bits : 5 - 5 (1 bit)

RUE0 : RX ULPS Escape lane 0
bits : 6 - 6 (1 bit)

PSS1 : PHY Stop State lane 1
bits : 7 - 7 (1 bit)

UAN1 : ULPS Active Not lane 1
bits : 8 - 8 (1 bit)


DSI_ISR0 (ISR0)

DSI Host Interrupt and Status Register 0
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_ISR0 DSI_ISR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AE0 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 PE0 PE1 PE2 PE3 PE4

AE0 : Acknowledge Error 0
bits : 0 - 0 (1 bit)

AE1 : Acknowledge Error 1
bits : 1 - 1 (1 bit)

AE2 : Acknowledge Error 2
bits : 2 - 2 (1 bit)

AE3 : Acknowledge Error 3
bits : 3 - 3 (1 bit)

AE4 : Acknowledge Error 4
bits : 4 - 4 (1 bit)

AE5 : Acknowledge Error 5
bits : 5 - 5 (1 bit)

AE6 : Acknowledge Error 6
bits : 6 - 6 (1 bit)

AE7 : Acknowledge Error 7
bits : 7 - 7 (1 bit)

AE8 : Acknowledge Error 8
bits : 8 - 8 (1 bit)

AE9 : Acknowledge Error 9
bits : 9 - 9 (1 bit)

AE10 : Acknowledge Error 10
bits : 10 - 10 (1 bit)

AE11 : Acknowledge Error 11
bits : 11 - 11 (1 bit)

AE12 : Acknowledge Error 12
bits : 12 - 12 (1 bit)

AE13 : Acknowledge Error 13
bits : 13 - 13 (1 bit)

AE14 : Acknowledge Error 14
bits : 14 - 14 (1 bit)

AE15 : Acknowledge Error 15
bits : 15 - 15 (1 bit)

PE0 : PHY Error 0
bits : 16 - 16 (1 bit)

PE1 : PHY Error 1
bits : 17 - 17 (1 bit)

PE2 : PHY Error 2
bits : 18 - 18 (1 bit)

PE3 : PHY Error 3
bits : 19 - 19 (1 bit)

PE4 : PHY Error 4
bits : 20 - 20 (1 bit)


DSI_LVCIDR (LVCIDR)

DSI Host LTDC VCID Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_LVCIDR DSI_LVCIDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCID

VCID : Virtual Channel ID
bits : 0 - 1 (2 bit)


DSI_ISR1 (ISR1)

DSI Host Interrupt and Status Register 1
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSI_ISR1 DSI_ISR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOHSTX TOLPRX ECCSE ECCME CRCE PSE EOTPE LPWRE GCWRE GPWRE GPTXE GPRDE GPRXE

TOHSTX : Timeout High-Speed Transmission
bits : 0 - 0 (1 bit)

TOLPRX : Timeout Low-Power Reception
bits : 1 - 1 (1 bit)

ECCSE : ECC Single-bit Error
bits : 2 - 2 (1 bit)

ECCME : ECC Multi-bit Error
bits : 3 - 3 (1 bit)

CRCE : CRC Error
bits : 4 - 4 (1 bit)

PSE : Packet Size Error
bits : 5 - 5 (1 bit)

EOTPE : EoTp Error
bits : 6 - 6 (1 bit)

LPWRE : LTDC Payload Write Error
bits : 7 - 7 (1 bit)

GCWRE : Generic Command Write Error
bits : 8 - 8 (1 bit)

GPWRE : Generic Payload Write Error
bits : 9 - 9 (1 bit)

GPTXE : Generic Payload Transmit Error
bits : 10 - 10 (1 bit)

GPRDE : Generic Payload Read Error
bits : 11 - 11 (1 bit)

GPRXE : Generic Payload Receive Error
bits : 12 - 12 (1 bit)


DSI_IER0 (IER0)

DSI Host Interrupt Enable Register 0
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_IER0 DSI_IER0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AE0IE AE1IE AE2IE AE3IE AE4IE AE5IE AE6IE AE7IE AE8IE AE9IE AE10IE AE11IE AE12IE AE13IE AE14IE AE15IE PE0IE PE1IE PE2IE PE3IE PE4IE

AE0IE : Acknowledge Error 0 Interrupt Enable
bits : 0 - 0 (1 bit)

AE1IE : Acknowledge Error 1 Interrupt Enable
bits : 1 - 1 (1 bit)

AE2IE : Acknowledge Error 2 Interrupt Enable
bits : 2 - 2 (1 bit)

AE3IE : Acknowledge Error 3 Interrupt Enable
bits : 3 - 3 (1 bit)

AE4IE : Acknowledge Error 4 Interrupt Enable
bits : 4 - 4 (1 bit)

AE5IE : Acknowledge Error 5 Interrupt Enable
bits : 5 - 5 (1 bit)

AE6IE : Acknowledge Error 6 Interrupt Enable
bits : 6 - 6 (1 bit)

AE7IE : Acknowledge Error 7 Interrupt Enable
bits : 7 - 7 (1 bit)

AE8IE : Acknowledge Error 8 Interrupt Enable
bits : 8 - 8 (1 bit)

AE9IE : Acknowledge Error 9 Interrupt Enable
bits : 9 - 9 (1 bit)

AE10IE : Acknowledge Error 10 Interrupt Enable
bits : 10 - 10 (1 bit)

AE11IE : Acknowledge Error 11 Interrupt Enable
bits : 11 - 11 (1 bit)

AE12IE : Acknowledge Error 12 Interrupt Enable
bits : 12 - 12 (1 bit)

AE13IE : Acknowledge Error 13 Interrupt Enable
bits : 13 - 13 (1 bit)

AE14IE : Acknowledge Error 14 Interrupt Enable
bits : 14 - 14 (1 bit)

AE15IE : Acknowledge Error 15 Interrupt Enable
bits : 15 - 15 (1 bit)

PE0IE : PHY Error 0 Interrupt Enable
bits : 16 - 16 (1 bit)

PE1IE : PHY Error 1 Interrupt Enable
bits : 17 - 17 (1 bit)

PE2IE : PHY Error 2 Interrupt Enable
bits : 18 - 18 (1 bit)

PE3IE : PHY Error 3 Interrupt Enable
bits : 19 - 19 (1 bit)

PE4IE : PHY Error 4 Interrupt Enable
bits : 20 - 20 (1 bit)


DSI_IER1 (IER1)

DSI Host Interrupt Enable Register 1
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSI_IER1 DSI_IER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOHSTXIE TOLPRXIE ECCSEIE ECCMEIE CRCEIE PSEIE EOTPEIE LPWREIE GCWREIE GPWREIE GPTXEIE GPRDEIE GPRXEIE

TOHSTXIE : Timeout High-Speed Transmission Interrupt Enable
bits : 0 - 0 (1 bit)

TOLPRXIE : Timeout Low-Power Reception Interrupt Enable
bits : 1 - 1 (1 bit)

ECCSEIE : ECC Single-bit Error Interrupt Enable
bits : 2 - 2 (1 bit)

ECCMEIE : ECC Multi-bit Error Interrupt Enable
bits : 3 - 3 (1 bit)

CRCEIE : CRC Error Interrupt Enable
bits : 4 - 4 (1 bit)

PSEIE : Packet Size Error Interrupt Enable
bits : 5 - 5 (1 bit)

EOTPEIE : EoTp Error Interrupt Enable
bits : 6 - 6 (1 bit)

LPWREIE : LTDC Payload Write Error Interrupt Enable
bits : 7 - 7 (1 bit)

GCWREIE : Generic Command Write Error Interrupt Enable
bits : 8 - 8 (1 bit)

GPWREIE : Generic Payload Write Error Interrupt Enable
bits : 9 - 9 (1 bit)

GPTXEIE : Generic Payload Transmit Error Interrupt Enable
bits : 10 - 10 (1 bit)

GPRDEIE : Generic Payload Read Error Interrupt Enable
bits : 11 - 11 (1 bit)

GPRXEIE : Generic Payload Receive Error Interrupt Enable
bits : 12 - 12 (1 bit)


DSI_FIR0 (FIR0)

DSI Host Force Interrupt Register 0
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DSI_FIR0 DSI_FIR0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FAE0 FAE1 FAE2 FAE3 FAE4 FAE5 FAE6 FAE7 FAE8 FAE9 FAE10 FAE11 FAE12 FAE13 FAE14 FAE15 FPE0 FPE1 FPE2 FPE3 FPE4

FAE0 : Force Acknowledge Error 0
bits : 0 - 0 (1 bit)

FAE1 : Force Acknowledge Error 1
bits : 1 - 1 (1 bit)

FAE2 : Force Acknowledge Error 2
bits : 2 - 2 (1 bit)

FAE3 : Force Acknowledge Error 3
bits : 3 - 3 (1 bit)

FAE4 : Force Acknowledge Error 4
bits : 4 - 4 (1 bit)

FAE5 : Force Acknowledge Error 5
bits : 5 - 5 (1 bit)

FAE6 : Force Acknowledge Error 6
bits : 6 - 6 (1 bit)

FAE7 : Force Acknowledge Error 7
bits : 7 - 7 (1 bit)

FAE8 : Force Acknowledge Error 8
bits : 8 - 8 (1 bit)

FAE9 : Force Acknowledge Error 9
bits : 9 - 9 (1 bit)

FAE10 : Force Acknowledge Error 10
bits : 10 - 10 (1 bit)

FAE11 : Force Acknowledge Error 11
bits : 11 - 11 (1 bit)

FAE12 : Force Acknowledge Error 12
bits : 12 - 12 (1 bit)

FAE13 : Force Acknowledge Error 13
bits : 13 - 13 (1 bit)

FAE14 : Force Acknowledge Error 14
bits : 14 - 14 (1 bit)

FAE15 : Force Acknowledge Error 15
bits : 15 - 15 (1 bit)

FPE0 : Force PHY Error 0
bits : 16 - 16 (1 bit)

FPE1 : Force PHY Error 1
bits : 17 - 17 (1 bit)

FPE2 : Force PHY Error 2
bits : 18 - 18 (1 bit)

FPE3 : Force PHY Error 3
bits : 19 - 19 (1 bit)

FPE4 : Force PHY Error 4
bits : 20 - 20 (1 bit)


DSI_FIR1 (FIR1)

DSI Host Force Interrupt Register 1
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DSI_FIR1 DSI_FIR1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTOHSTX FTOLPRX FECCSE FECCME FCRCE FPSE FEOTPE FLPWRE FGCWRE FGPWRE FGPTXE FGPRDE FGPRXE

FTOHSTX : Force Timeout High-Speed Transmission
bits : 0 - 0 (1 bit)

FTOLPRX : Force Timeout Low-Power Reception
bits : 1 - 1 (1 bit)

FECCSE : Force ECC Single-bit Error
bits : 2 - 2 (1 bit)

FECCME : Force ECC Multi-bit Error
bits : 3 - 3 (1 bit)

FCRCE : Force CRC Error
bits : 4 - 4 (1 bit)

FPSE : Force Packet Size Error
bits : 5 - 5 (1 bit)

FEOTPE : Force EoTp Error
bits : 6 - 6 (1 bit)

FLPWRE : Force LTDC Payload Write Error
bits : 7 - 7 (1 bit)

FGCWRE : Force Generic Command Write Error
bits : 8 - 8 (1 bit)

FGPWRE : Force Generic Payload Write Error
bits : 9 - 9 (1 bit)

FGPTXE : Force Generic Payload Transmit Error
bits : 10 - 10 (1 bit)

FGPRDE : Force Generic Payload Read Error
bits : 11 - 11 (1 bit)

FGPRXE : Force Generic Payload Receive Error
bits : 12 - 12 (1 bit)



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