\n
address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x30 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x70 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
System Power-down Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XTL12M_EN : 4~24 MHz External High Speed Crystal Oscillator (HXT) Enable Bit (Write Protect)
The bit default value is set by flash controller user configuration register CONFIG0 [26:24]. When the default clock source is from 4~24 MHz external high speed crystal oscillator, this bit is set to 1 automatically.
Note: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
4 ~ 24 MHz external high speed crystal oscillator (HXT) Disabled
#1 : 1
4 ~ 24 MHz external high speed crystal oscillator (HXT) Enabled
End of enumeration elements list.
OSC22M_EN : 22.1184 MHz Internal High Speed RC Oscillator (HIRC) Enable Bit (Write Protect)
Note: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
22.1184 MHz internal high speed RC oscillator (HIRC) Disabled
#1 : 1
22.1184 MHz internal high speed RC oscillator (HIRC) Enabled
End of enumeration elements list.
OSC10K_EN : 10 KHz Internal Low Speed RC Oscillator (LIRC) Enable Bit (Write Protect)
Note: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
10 kHz internal low speed RC oscillator (LIRC) Disabled
#1 : 1
10 kHz internal low speed RC oscillator (LIRC) Enabled
End of enumeration elements list.
PD_WU_DLY : Wake-Up Delay Counter Enable Bit (Write Protect)
When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.
The delayed clock cycle is 4096 clock cycles when chip work at external 4~24 MHz high speed crystal, and 256 clock cycles when chip work at internal 22.1184 MHz high speed oscillator.
Note: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock cycles delay Disabled
#1 : 1
Clock cycles delay Enabled
End of enumeration elements list.
PD_WU_INT_EN : Power-Down Mode Wake-Up Interrupt Enable Bit (Write Protect)
Note1: The interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high.
Note2: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Power-down mode wake-up interrupt Disabled
#1 : 1
Power-down mode wake-up interrupt Enabled
End of enumeration elements list.
PD_WU_STS : Power-Down Mode Wake-Up Interrupt Status
Set by Power-down wake-up event , it indicates that resume from Power-down mode .
The flag is set if the GPIO, UART, WDT, I2C, TIMER, or BOD wake-up occurred.
Write 1 to clear the bit to 0.
Note: This bit is working only if PD_WU_INT_EN (PWRCON[5]) set to 1.
bits : 6 - 6 (1 bit)
access : read-write
PWR_DOWN_EN : System Power-Down Enable Bit (Write Protect)
When this bit is set to 1, Power-down mode is enabled and chip Power-down behavior will depends on the PD_WAIT_CPU bit
(a) If the PD_WAIT_CPU is 0, the chip enters Power-down mode immediately after the PWR_DOWN_EN bit set.
(b) if the PD_WAIT_CPU is 1, the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode (recommend)
When chip wakes up from Power-down mode, this bit is cleared by hardware. User needs to set this bit again for next Power-down.
In Power-down mode, 4~24 MHz external high speed crystal oscillator and the 22.1184 MHz internal high speed RC oscillator will be disabled in this mode, but the 10 kHz internal low speed oscillator is not controlled by Power-down mode.
In Power- down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from the internal 10 kHz low speed oscillator.
Note: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip operating normally or chip in Idle mode because of WFI command
#1 : 1
Chip enters Power-down mode instantly or waits CPU sleep command WFI
End of enumeration elements list.
PD_WAIT_CPU : Power-Down Entry Condition Control (Write Protect)\nNote: This bit is the protected bit, and programming it needs to write "59h", "16h", and "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip enters Power-down mode when the PWR_DOWN_EN bit is set to 1
#1 : 1
Chip enters Power- down mode when the both PD_WAIT_CPU and PWR_DOWN_EN bits are set to 1 and CPU run WFI instruction
End of enumeration elements list.
Clock Source Select Control Register 0
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLK_S : HCLK Clock Source Select (Write Protect)\nBefore clock switching, the related clock sources (both pre-select and new-select) must be enabled\nThe 3-bit default value is reloaded from the value of CFOSC (CONFIG0[26:24]) in user configuration register of Flash controller by any reset. Therefore the default value is either 000b or 111b.\nThese bits are protected bit. It means programming this bit needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.\nNote: This bit is the protected bit, and programming it needs to write "59h", "16h", and "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from 4~24 MHz external high speed crystal oscillator clock
#001 : 1
Reserved
#010 : 2
Clock source from PLL clock
#011 : 3
Clock source from 10 kHz internal low speed RC oscillator clock
#111 : 7
Clock source from 22.1184 MHz internalhigh speed RC oscillator clock
End of enumeration elements list.
STCLK_S : Cortex-M0 SysTick Clock Source Select (Write Protect)\n
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from 4~24 MHz external high speed crystal oscillator clock
#001 : 1
Reserved
#010 : 2
Clock source from 4~24 MHz external high speed crystal oscillator clock/2
#011 : 3
Clock source from HCLK/2
#111 : 7
Clock source from 22.1184 MHz internal high speed RC oscillator clock/2
End of enumeration elements list.
Clock Source Select Control Register 1
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_S : Watchdog Timer Clock Source Select (Write Protect)\nNote: This bit is the protected bit, and programming it needs to write "59h", "16h", and "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Reserved
#01 : 1
Reserved
#10 : 2
Clock source from HCLK/2048 clock
#11 : 3
Clock source from 10 kHz internal low speed RC oscillator clock
End of enumeration elements list.
ADC_S : ADC Clock Source Select\n
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from 4~24 MHz external high speed crystal oscillator clock
#01 : 1
Clock source from PLL clock
#10 : 2
Clock source from HCLK
#11 : 3
Clock source from 22.1184 MHz internal high speed RC oscillator clock
End of enumeration elements list.
SPI0_S : SPI0 Clock Source Selection\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source from PLL clock
#1 : 1
Clock source from HCLK
End of enumeration elements list.
TMR0_S : TIMER0 Clock Source Selection\n
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from 4~24 MHz external high speed crystal oscillator clock
#001 : 1
Reserved
#010 : 2
Clock source from HCLK
#011 : 3
Clock source from external trigger
#101 : 5
Clock source from 10 kHz internal low speed RC oscillator clock
#111 : 7
Clock source from 22.1184 MHz internal high speed RC oscillator clock
End of enumeration elements list.
TMR1_S : TIMER1 Clock Source Selection\n
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from 4~24 MHz external high speed crystal oscillator clock
#001 : 1
Reserved
#010 : 2
Clock source from HCLK
#011 : 3
Clock source from external trigger
#101 : 5
Clock source from 10 kHz internal low speed RC oscillator clock
#111 : 7
Clock source from 22.1184 MHz internal high speed RC oscillator clock
End of enumeration elements list.
TMR2_S : TIMER2 Clock Source Selection\n
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external 4~24 MHz high speed crystal oscillator clock
#001 : 1
Reserved
#010 : 2
Clock source from HCLK
#011 : 3
Clock source from external trigger
#101 : 5
Clock source from internal 10 kHz low speed RC oscillator clock
#111 : 7
Clock source from internal 22.1184 MHz high speed RC oscillator clock
End of enumeration elements list.
TMR3_S : TIMER3 Clock Source Selection\n
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from 4~24 MHz external high speed crystal oscillator clock
#001 : 1
Reserved
#010 : 2
Clock source from HCLK
#011 : 3
Clock source from external trigger
#101 : 5
Clock source from 10 kHz internal low speed RC oscillator clock
#111 : 7
Clock source from 22.1184 MHz internal high speed RC oscillator clock
End of enumeration elements list.
UART_S : UART Clock Source Selection\n
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from 4~24 MHz external high speed crystal oscillator clock
#01 : 1
Clock source from PLL clock
#11 : 3
Clock source from 22.1184 MHz internal high speed RC oscillator clock
End of enumeration elements list.
Clock Divider Number Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLK_N : HCLK Clock Divide Number From HCLK Clock Source\n
bits : 0 - 3 (4 bit)
access : read-write
UART_N : UART Clock Divide Number From UART Clock Source\n
bits : 8 - 11 (4 bit)
access : read-write
ADC_N : ADC Clock Divide Number From ADC Clock Source\n
bits : 16 - 23 (8 bit)
access : read-write
Clock Source Select Control Register 2
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRQDIV_S : Clock Divider Clock Source Selection\n
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from 4~24 MHz external high speed crystal oscillator clock
#01 : 1
Reserved
#10 : 2
Clock source from HCLK
#11 : 3
Clock source from 22.1184 MHz internal high speed RC oscillator clock
End of enumeration elements list.
WWDT_S : Window Watchdog Timer Clock Source Selection\n
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#10 : 2
Clock source from HCLK/2048 clock
#11 : 3
Clock source from 10 kHz internal low speed RC oscillator clock
End of enumeration elements list.
PLL Control Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FB_DV : PLL Feedback Divider Control Bits\nRefer to the formulas below the table.
bits : 0 - 8 (9 bit)
access : read-write
IN_DV : PLL Input Divider Control Bits\nRefer to the formulas below the table.
bits : 9 - 13 (5 bit)
access : read-write
OUT_DV : PLL Output Divider Control Bits\nRefer to the formulas below the table.
bits : 14 - 15 (2 bit)
access : read-write
PD : Power-Down Mode\nIf the PWR_DOWN_EN bit is set to 1 in PWRCON register, the PLL will enter Power-down mode too.\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL is in Normal mode
#1 : 1
PLL is in Power-down mode (default)
End of enumeration elements list.
BP : PLL Bypass Control\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL is in Normal mode (default)
#1 : 1
PLL clock output is same as PLL source clock input
End of enumeration elements list.
OE : PLL OE (FOUT Enable) Pin Control\n
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL FOUT Enabled
#1 : 1
PLL FOUT is fixed low
End of enumeration elements list.
PLL_SRC : PLL Source Clock Selection\n
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL source clock from 4~24 MHz external high speed crystal oscillator
#1 : 1
PLL source clock from 22.1184 MHz internal high speed RC oscillator
End of enumeration elements list.
Frequency Divider Control Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSEL : Divider Output Frequency Selection Bits\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FSEL[3:0].
bits : 0 - 3 (4 bit)
access : read-write
DIVIDER_EN : Frequency Divider Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frequency Divider function Disabled
#1 : 1
Frequency Divider function Enabled
End of enumeration elements list.
DIVIDER1 : Frequency Divider One Enable Bit\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frequency divider will output clock with source frequency divided by FSEL
#1 : 1
Frequency divider will output clock with source frequency
End of enumeration elements list.
APB Devices Clock Enable Control Register 1
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART3_EN : UART3 Clock Enable Bit\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART3 clock Disabled
#1 : 1
UART3 clock Enabled
End of enumeration elements list.
UART4_EN : UART4 Clock Enable Bit\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART4 clock Disabled
#1 : 1
UART4 clock Enabled
End of enumeration elements list.
UART5_EN : UART5 Clock Enable Bit\n
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART5 clock Disabled
#1 : 1
UART5 clock Enabled
End of enumeration elements list.
PWM0_EN : PWM0 Clock Enable Bit\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM0 clock Disabled
#1 : 1
PWM0 clock Enabled
End of enumeration elements list.
PWM1_EN : PWM1 Clock Enable Bit\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM1 clock Disabled
#1 : 1
PWM1 clock Enabled
End of enumeration elements list.
BPWM0_EN : BPWM0 Clock Enable Bit\n
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM0 clock Disabled
#1 : 1
BPWM0 clock Enabled
End of enumeration elements list.
BPWM1_EN : BPWM1 Clock Enable Bit\n
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM1 clock Disabled
#1 : 1
BPWM1 clock Enabled
End of enumeration elements list.
Clock Source Select Control Register 3
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM0_S : PWM0 Clock Source Selection\nThe Engine clock source of PWM0 is defined by PWM0_S.\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source from PLL clock
#1 : 1
Clock source from PCLK
End of enumeration elements list.
PWM1_S : PWM1 Clock Source Selection\nThe Engine clock source of PWM1 is defined by PWM1_S.\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source from PLL clock
#1 : 1
Clock source from PCLK
End of enumeration elements list.
BPWM0_S : BPWM0 Clock Source Selection\nThe Engine clock source of BPWM0 is defined by BPWM0_S.\n
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source from PLL clock
#1 : 1
Clock source from PCLK
End of enumeration elements list.
BPWM1_S : BPWM1 Clock Source Selection\nThe Engine clock source of BPWM1 is defined by BPWM1_S.\n
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source from PLL clock
#1 : 1
Clock source from PCLK
End of enumeration elements list.
AHB Devices Clock Enable Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISP_EN : Flash ISP Controller Clock Enable Bit\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flash ISP peripherial clock Disabled
#1 : 1
Flash ISP peripherial clock Enabled
End of enumeration elements list.
Clock Fail Detector Control Register
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HXTFDEN : HXT Clock Fail Detector Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
HXT clock Fail detector Disabled
#1 : 1
HXT clock Fail detector Enabled
End of enumeration elements list.
HXTFIEN : HXT Clock Fail Interrupt Enable Bit\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
HXT clock Fail interrupt Disabled
#1 : 1
HXT clock Fail interrupt Enabled
End of enumeration elements list.
HXTFQDEN : HXT Clock Frequency Monitor Enable Bit\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
HXT clock frequency monitor Disabled
#1 : 1
HXT clock frequency monitor Enabled
End of enumeration elements list.
HXTFQIEN : HXT Clock Frequency Monitor Interrupt Enable Bit\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
HXT clock frequency monitor fail interrupt Disabled
#1 : 1
HXT clock frequency monitor fail interrupt Enabled
End of enumeration elements list.
Clock Fail Detector Status Register
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HXTFIF : HXT Clock Fail Interrupt Flag\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
HXT clock normal
#1 : 1
HXT clock stop (write "1" to clear)
End of enumeration elements list.
HXTFQIF : HXT Clock Frequency Monitor Interrupt Flag\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
HXT clock normal
#1 : 1
HXT clock frequency abnormal (write "1" to clear)
End of enumeration elements list.
Clock Frequency Detector Upper Boundary Register
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPERBD : HXT Clock Frequency Detector Upper Boundary\nThe bits define the high value of frequency monitor window.\nWhen HXT frequency monitor value higher than this register, the HXT frequency detect fail interrupt flag will set to 1.
bits : 0 - 9 (10 bit)
access : read-write
Clock Frequency Detector Low Boundary Register
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOWERBD : HXT Clock Frequency Detector Low Boundary\nThe bits define the low value of frequency monitor window.\nWhen HXT frequency monitor values lower than this register, the HXT frequency detect fail interrupt flag will set to 1.
bits : 0 - 9 (10 bit)
access : read-write
APB Devices Clock Enable Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_EN : Watchdog Timer Clock Enable Bit (Write Protect)\nNote: This bit is the protected bit, and programming it needs to write "59h", "16h", and "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Watchdog Timer clock Disabled
#1 : 1
Watchdog Timer clock Enabled
End of enumeration elements list.
TMR0_EN : Timer0 Clock Enable Bit\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer0 clock Disabled
#1 : 1
Timer0 clock Enabled
End of enumeration elements list.
TMR1_EN : Timer1 Clock Enable Bit\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer1 clock Disabled
#1 : 1
Timer1 clock Enabled
End of enumeration elements list.
TMR2_EN : Timer2 Clock Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer2 clock Disabled
#1 : 1
Timer2 clock Enabled
End of enumeration elements list.
TMR3_EN : Timer3 Clock Enable Bit\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer3 clock Disabled
#1 : 1
Timer3 clock Enabled
End of enumeration elements list.
FDIV_EN : Frequency Divider Output Clock Enable Bit\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
FDIV clock Disabled
#1 : 1
FDIV clock Enabled
End of enumeration elements list.
I2C0_EN : I2C0 Clock Enable Bit\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C0 clock Disabled
#1 : 1
I2C0 clock Enabled
End of enumeration elements list.
I2C1_EN : I2C1 Clock Enable Bit\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C1 clock Disabled
#1 : 1
I2C1 clock Enabled
End of enumeration elements list.
SPI0_EN : SPI0 Clock Enable Bit\n
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI0 clock Disabled
#1 : 1
SPI0 clock Enabled
End of enumeration elements list.
UART0_EN : UART0 Clock Enable Bit\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART0 clock Disabled
#1 : 1
UART0 clock Enabled
End of enumeration elements list.
UART1_EN : UART1 Clock Enable Bit\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART1 clock Disabled
#1 : 1
UART1 clock Enabled
End of enumeration elements list.
UART2_EN : UART2 Clock Enable Bit\n
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART2 clock Disabled
#1 : 1
UART2 clock Enabled
End of enumeration elements list.
ADC_EN : Analog-Digital-Converter (ADC) Clock Enable Bit\n
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADC clock Disabled
#1 : 1
ADC clock Enabled
End of enumeration elements list.
Clock status monitor Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XTL12M_STB : 4~24 MHz External High Speed Crystal Oscillator (HXT) Clock Source Stable Flag (Read Only)\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled
#1 : 1
4~24 MHz external high speed crystal oscillator (HXT) clock is stable and enabled
End of enumeration elements list.
PLL_STB : Internal PLL Clock Source Stable Flag (Read Only)\n
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal PLL clock is not stable or disabled
#1 : 1
Internal PLL clock is stable in normal mode
End of enumeration elements list.
OSC10K_STB : Internal 10 KHz Low Speed Oscillator (LIRC) Clock Source Stable Flag (Read Only)\n
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled
#1 : 1
10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled
End of enumeration elements list.
OSC22M_STB : 22.1184 MHz Internal High Speed RC Oscillator (HIRC) Clock Source Stable Flag (Read Only)\n
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
22.1184 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled
#1 : 1
22.1184 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled
End of enumeration elements list.
CLK_SW_FAIL : Clock Switching Fail Flag (Read Only)\nThis bit is an index that if current system clock source is match as user defined at HCLK_S (CLKSEL[2:0]). When user switch system clock, the system clock source will keep old clock until the new clock is stable. During the period that waiting new clock stable, this bit will be an index shows system clock source is not match as user wanted.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
Clock switching success
#1 : 1
Clock switching failure
End of enumeration elements list.
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