\n
address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x3C Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
I2C Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AA : Assert Acknowledge Control\n
bits : 2 - 2 (1 bit)
access : read-write
SI : I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register, the SI flag is set by hardware, and if bit EI (I2CON [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.
bits : 3 - 3 (1 bit)
access : read-write
STO : I2C STOP Control\nIn Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In a slave mode, setting STO resets I2C hardware to the defined "not addressed" slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device.
bits : 4 - 4 (1 bit)
access : read-write
STA : I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
bits : 5 - 5 (1 bit)
access : read-write
ENS1 : I2C Controller Enable Bit\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
EI : Interrupt Enable Bit\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C interrupt Disabled
#1 : 1
I2C interrupt Enabled
End of enumeration elements list.
I2C Clock Divided Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2CLK : I2C Clock Divided Register\nNote: The minimum value of I2CLK is 4.
bits : 0 - 7 (8 bit)
access : read-write
I2C Time-out Counter Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIF : Time-Out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit EI (I2CON[7]) is set to 1.\nNote: Write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write
DIV4 : Time-Out Counter Input Clock Divided By 4\nWhen Enabled, The time-out period is extend 4 times.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
ENTI : Time-Out Counter Enable Bit \nWhen Enabled, the 14-bit time-out counter will start counting when SI (I2CON[3]) is clear. Setting flag SI SI(I2CON[3]) to high will reset counter and re-start up counting after SI SI(I2CON[3]) is cleared.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C Slave Address Mask Register0
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2CADM : I2C Address Mask Register\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
bits : 1 - 7 (7 bit)
access : read-write
Enumeration:
0 : 0
Mask Disabled (the received corresponding register bit should be exact the same as address register.)
1 : 1
Mask Enabled (the received corresponding address bit is don't care.)
End of enumeration elements list.
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C Wake-up Control Register
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WKUPEN : I2C Wake-Up Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C wake-up function Disabled
#1 : 1
I2C wake-up function Enabled
End of enumeration elements list.
I2C Slave Address Register0
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GC : General Call Function\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
General Call Function Disabled
#1 : 1
General Call Function Enabled
End of enumeration elements list.
I2CADDR : I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.
bits : 1 - 7 (7 bit)
access : read-write
I2C Wake-up Status Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WKUPIF : I2C Wake-Up Flag\nNote: Software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip is not woken-up from Power-down mode by I2C
#1 : 1
Chip is woken-up from Power-down mode by I2C
End of enumeration elements list.
I2C Data Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2CDAT : I2C Data Register\nThis field is located with the 8-bit transferred data of I2C serial port.
bits : 0 - 7 (8 bit)
access : read-write
I2C Status Register
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
I2CSTATUS : I2C Status Register\nThere are 26 possible status codes. \nWhen I2CSTATUS contains 0xF8, no serial interrupt is requested. \nIn addition, states 0x00 stands for a Bus Error. A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame. Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit.
bits : 0 - 7 (8 bit)
access : read-only
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