CPUID

SCR

SHPR2

SHPR3

ICSR

AIRCR

Revision : Reads as 0x0.
bits : 0 - 3 (4 bit)
access : read-only

Partno : Reads as 0xC20 corresponding to Cortex-M0
bits : 4 - 15 (12 bit)
access : read-only

Constant : Read as 0xC corresponding to ARMv6-M architecture.
bits : 16 - 19 (4 bit)
access : read-only

Variant : Read as 0x0.
bits : 20 - 23 (4 bit)
access : read-only

Implementer : None
bits : 24 - 31 (8 bit)
access : read-only

SLEEPONEXIT : Sleep-on-Exit Enable\nThis bit controls sleep-on-exit when returning from Handler mode to Thread mode:\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SLEEPDEEP : Deep Sleep Mode Enable\nThis bit controls whether the processor uses sleep or deep sleep as its low power mode:
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SEVONPEND : Send Event on Pending Bit\nWhen an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRI_11 : Priority of System Handler 11, SVCall\n'0' denotes the highest priority and '3' denotes the lowest priority
bits : 30 - 31 (2 bit)
access : read-write

PRI_14 : Priority of System Handler 14, PendSV\n'0' denotes the highest priority and '3' denotes the lowest priority
bits : 22 - 23 (2 bit)
access : read-write

PRI_15 : Priority of System Handler 15, SysTick\n'0' denotes the highest priority and '3' denotes the lowest priority
bits : 30 - 31 (2 bit)
access : read-write

VECTACTIVE : Vector active indicator. (Read only)\nThis field contains the active exception number:
bits : 0 - 5 (6 bit)
access : read-only

Enumeration:

End of enumeration elements list.

VECTPENDING : Vector pending indicator. (Read only)\nThis field indicates the exception number of the highest priority pending enabled exception:
bits : 12 - 17 (6 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ISRPENDING : Interrupt pending flag. (Read only)\nIndicates if an external configurable (NVIC generated) interrupt is pending.
bits : 22 - 22 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PENDSTCLR : SysTick exception clear-pending bit. (Write only)\nWrite:
bits : 25 - 25 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

PENDSTSET : SysTick exception set-pending bit.\nWrite:
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PENDSVCLR : PendSV clear-pending bit. (Write only)\nWrite:
bits : 27 - 27 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

PENDSVSET : PendSV set-pending bit.\nWrite:\nWriting 1 to this bit is the only way to set the PendSV exception state to pending.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NMIPENDSET : NMI set-pending bit.\nWrite:\nBecause NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYSRESETREQ : System reset request. (Write only)
bits : 2 - 2 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

VECTKEY : Register key. (Write only)\nReads as Unknown. On writes, write 0x05FA to VECTKEY, otherwise the write is ignored.
bits : 16 - 31 (16 bit)
access : write-only