EPWM_NPCTL (NPCTL)

EPWM_CMPDAT0 (CMPDAT0)

EPWM_CMPDAT1 (CMPDAT1)

EPWM_CMPDAT2 (CMPDAT2)

EPWM_CMPDAT3 (CMPDAT3)

EPWM_CMPDAT4 (CMPDAT4)

EPWM_CMPDAT5 (CMPDAT5)

EPWM_CNT (CNT)

EPWM_CLKDIV (CLKDIV)

EPWM_INTEN (INTEN)

EPWM_INTSTS (INTSTS)

EPWM_RESDLY (RESDLY)

EPWM_BRKCTL (BRKCTL)

EPWM_DTCTL (DTCTL)

EPWM_ADCTCTL0 (ADCTCTL0)

EPWM_ADCTCTL1 (ADCTCTL1)

EPWM_ADCTSTS0 (ADCTSTS0)

EPWM_ADCTSTS1 (ADCTSTS1)

EPWM_PHCHG (PHCHG)

EPWM_PHCHGNXT (PHCHGNXT)

EPWM_CTL (CTL)

EPWM_PHCHGALT (PHCHGALT)

EPWM_IFA (IFA)

EPWM_PERIOD (PERIOD)

NEGPOLAR : PWM Negative Polarity Control\nThe register bit controls polarity/active state of real PWM output.\n
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMP : PWM Comparator Register CMP determines the PWM Duty. Edge-aligned mode: where xy, could be 01, 23, 45 depending on the selected PWM channel. Note: Any write to CMPn will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write

CMPU : PWM Comparator Register for UP Counter in Center-aligned Asymmetric Mode CMPU PERIOD: @ up counter PWM output is keep to Max. duty.
bits : 16 - 31 (16 bit)
access : read-write

CNT : PWM Counter Register\nUser can monitor CNT to know the current value in 16-bit down counter.
bits : 0 - 15 (16 bit)
access : read-only

CNTDIR : PWM Counter (Up/Down) Direction\n
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CLKDIV : EPWM Clock Divider (9 Step Divider)\nSelect clock input for PWM timer\n
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PIEN : PWM Channel 0 Period Interrupt Enable Bit\nfor Edge-aligned and Center-aligned \n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPUIEN0 : PWM Channel 0 UP Interrupt Enable\nUP for Center-aligned only\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPUIEN1 : PWM Channel 1 UP Interrupt Enable\nUP for Center-aligned only\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPUIEN2 : PWM Channel 2 UP Interrupt Enable Bit \nUP for Center-aligned only\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPUIEN3 : PWM Channel 3 UP Interrupt Enable\nUP for Center-aligned only\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPUIEN4 : PWM Channel 4 UP Interrupt Enable Bit\nUP for Center-aligned only\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPUIEN5 : PWM Channel 5 UP Interrupt Enable Bit \nUP for Center-aligned only\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRK0IEN : Enable Fault Brake0 Interrupt\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRK1IEN : Enable Fault Brake1 Interrupt\n
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CIEN : PWM Central Interrupt Enable Bit\nfor Center-aligned only \n
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPDIEN0 : PWM Channel 0 DOWN Interrupt Enable Bit\nDOWN for Edge-aligned and Center-aligned\n
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPDIEN1 : PWM Channel 1 DOWN Interrupt Enable\nDOWN for Edge-aligned and Center-aligned\n
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPDIEN2 : PWM Channel 2 DOWN Interrupt Enable Bit\nDOWN for Edge-aligned and Center-aligned\n
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPDIEN3 : PWM Channel 3 DOWN Interrupt Enable Bit\nDOWN for Edge-aligned and Center-aligned\n
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPDIEN4 : PWM Channel 4 DOWN Interrupt Enable Bit\nDOWN for Edge-aligned and Center-aligned\n
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPDIEN5 : PWM Channel 5 DOWN Interrupt Enable Bit\nDOWN for Edge-aligned and Center-aligned\n
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PIF : PWM Channel 0 Period Interrupt Flag\nFlag is set by hardware when PWM_PERIOD0down counter reaches zero. Software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

CMPUIF0 : PWM Channel 0 UP Interrupt Flag\nFlag is set by hardware when a channel 0 PWM UP counter reaches PWM_CMPDAT0. Software can write 1 to clear this bit.
bits : 8 - 8 (1 bit)
access : read-write

CMPUIF1 : PWM Channel 1 UP Interrupt Flag\nFlag is set by hardware when a channel 1 PWM UP counter reaches PWM_CMPDAT01. Software can write 1 to clear this bit.
bits : 9 - 9 (1 bit)
access : read-write

CMPUIF2 : PWM Channel 2 UP Interrupt Flag\nFlag is set by hardware when a channel 2 PWM UP counter reaches PWM_CMPDAT02. Software can write 1 to clear this bit.
bits : 10 - 10 (1 bit)
access : read-write

CMPUIF3 : PWM Channel 3 UP Interrupt Flag\nFlag is set by hardware when a channel 3 PWMUP counter reaches PWM_CMPDAT03. Software can write 1 to clear this bit.
bits : 11 - 11 (1 bit)
access : read-write

CMPUIF4 : PWM Channel 4 UP Interrupt Flag\nFlag is set by hardware when a channel 4 PWM UP counter reaches PWM_CMPDAT04. Software can write 1 to clear this bit.
bits : 12 - 12 (1 bit)
access : read-write

CMPUIF5 : PWM Channel 5 UP Interrupt Flag\nFlag is set by hardware when a channel 5 PWM UP counter reaches PWM_CMPDAT05. Software can write 1 to clear this bit.
bits : 13 - 13 (1 bit)
access : read-write

BRK0IF : PWM Brake0 Flag\nNote: Software can write 1 to clear this bit.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRK1IF : PWM Brake1 Flag\nNote: Software can write 1 to clear this bit.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CIF : PWM Channel 0 Central Interrupt Flag\nFlag is set by hardware when a channel 0 PWM rise counter reaches PWM_PERIOD0. Software can write 1 to clear this bit.
bits : 18 - 18 (1 bit)
access : read-write

CMPDIF0 : PWM Channel 0 DOWN Interrupt Flag\nFlag is set by hardware when a channel 0 PWM DOWN counter reaches PWM_CMPDAT0. Software can write 1 to clear this bit.
bits : 24 - 24 (1 bit)
access : read-write

CMPDIF1 : PWM Channel 1 DOWN Interrupt Flag\nFlag is set by hardware when a channel 1 PWM DOWN counter reaches PWM_CMPDAT01. Software can write 1 to clear this bit.
bits : 25 - 25 (1 bit)
access : read-write

CMPDIF2 : PWM Channel 2 DOWN Interrupt Flag\nFlag is set by hardware when a channel 2 PWM DOWN counter reaches PWM_CMPDAT2. Software can write 1 to clear this bit.
bits : 26 - 26 (1 bit)
access : read-write

CMPDIF3 : PWM Channel 3 DOWN Interrupt Flag\nFlag is set by hardware when a channel 3 PWM DOWN counter reaches PWM_CMPDAT03. Software can write 1 to clear this bit.
bits : 27 - 27 (1 bit)
access : read-write

CMPDIF4 : PWM Channel 4 DOWN Interrupt Flag\nFlag is set by hardware when a channel 4 PWM DOWN counter reaches PWM_CMPDAT04. Software can write 1 to clear this bit.
bits : 28 - 28 (1 bit)
access : read-write

CMPDIF5 : PWM Channel 5 DOWN Interrupt Flag\nFlag is set by hardware when a channel 5 PWM DOWN counter reaches PWM_CMPDAT05. Software can write 1 to clear this bit.
bits : 29 - 29 (1 bit)
access : read-write

DELAY : PWM BRK Low Voltage Detect Resume Delay\n12 bits Down-Counter
bits : 0 - 11 (12 bit)
access : read-write

BRK0EN : Enable BKP0 Pin Trigger Fault Brake Function 0\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRK1EN : Enable BKP1 Pin Trigger Fault Brake Function 1\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BK0CMP0EN : BRK0 Source From ACMP0 Enable\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BK0CMP1EN : BRK0 Source From ACMP1 Enable\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BK0ADCEN : BRK0 Source From ADC Enable\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BK0PEN : BRK0 Source From External Pin Enable\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SWBRK : Software Break\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BK1CMP0EN : BRK1 Source From ACMP0 Enable\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BK1CMP1EN : BRK1 Source From ACMP1 Enable\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BK1ADCEN : BRK1 Source From ADC Enable\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BK1PEN : BRK1 Source From External Pin Enable\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVDBKEN : Low-level Detection Trigger PWM Brake Function 1 Enable\n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVDTYPE : Low-level Detection Resume Type\n
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKOD0 : PWM Channel 0 Brake Output Select Register\n
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKOD1 : PWM Channel 1 Brake Output Select Register\n
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKOD2 : PWM Channel 2 Brake Output Select Register\n
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKOD3 : PWM Channel 3 Brake Output Select Register\n
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKOD4 : PWM Channel 4 Brake Output Select Register\n
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKOD5 : PWM Channel 5 Brake Output Select Register\n
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NFPEN : Noise Filter for External Brake Input Pin (BRK_I) Enable\n
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DTCNT01 : Dead-zone Interval Register for Pair of Channel0 and Channel1 (PWM0 and PWM1 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding PWM_CLKDIV bits.
bits : 0 - 7 (8 bit)
access : read-write

DTCNT23 : Dead-zone Interval Register for Pair of Channel2 and Channel3 (PWM2 and PWM3 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding PWM_CLKDIV bits.
bits : 8 - 15 (8 bit)
access : read-write

DTCNT45 : Dead-zone Interval Register for Pair of Channel4 and Channel5 (PWM4 and PWM5 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding PWM_CLKDIV bits.
bits : 16 - 23 (8 bit)
access : read-write

CDTRGEN0 : Enable PWM Trigger ADC Function While Channel0's Counter Matching PWM_CMPDAT0in Down-count Direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ZPTRGEN : Enable PWM Trigger ADC Function While Channel0's Counter Matching 0 (Zero Point)\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CUTRGEN0 : Enable PWM Trigger ADC Function While Channel0's Counter Matching PWM_CMPDAT0in Up-count Direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PTRGEN : Enable PWM Trigger ADC Function While Channel0's Counter Matching Period\nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CDTRGEN1 : Enable PWM Trigger ADC Function While Channel1's Counter Matching CMP1 in Down-count Direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CUTRGEN1 : Enable PWM Trigger ADC Function While Channel1's Counter Matching CMP1 In Up-count Direction Note: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CDTRGEN2 : Enable PWM Trigger ADC Function While Channel2's Counter Matching CMP2 in Down-count Direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CUTRGEN2 : Enable PWM Trigger ADC Function While Channel2's Counter Matching CMP2 In Up-count Direction Note: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CDTRGEN3 : Enable PWM Trigger ADC Function While Channel3's Counter Matching CMP3 in Down-count Direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CUTRGEN3 : Enable PWM Trigger ADC Function While Channel3's Counter Matching CMP3 in Up-count Direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CDTRGEN4 : Enable PWM Trigger ADC Function While Channel4's Counter Matching CMP4 in Down-count Direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CUTRGEN4 : Enable PWM Trigger ADC Function While Channel4's Counter Matching CMP4 in Up-count Direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CDTRGEN5 : Enable PWM Trigger ADC Function While Channel5's Counter Matching CMP5 in Down-count Direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CUTRGEN5 : Enable PWM Trigger ADC Function While Channel5's Counter Matching CMP5 in Up-count Direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CDTRGF0 : ADC Trigger Flag by Counting Down to CMP\nNote: Software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

ZPTRGF : ADC Trigger Flag By Counting to 0 (Zero Point) Note: Software can write 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write

CUTRGF0 : ADC Trigger Flag by Counting Up to CMP\nNote: Software can write 1 to clear this bit.
bits : 2 - 2 (1 bit)
access : read-write

PTRGF : ADC Trigger Flag by Period \nNote: Software can write 1 to clear this bit.
bits : 3 - 3 (1 bit)
access : read-write

CDTRGF1 : ADC Trigger Flag by Counting Down to CMP\nNote: Software can write 1 to clear this bit.
bits : 8 - 8 (1 bit)
access : read-write

CUTRGF1 : ADC Trigger Flag by Counting Up to CMP\nNote: Software can write 1 to clear this bit.
bits : 10 - 10 (1 bit)
access : read-write

CDTRGF2 : ADC Trigger Flag by Counting Down to CMP \nNote: Software can write 1 to clear this bit.
bits : 16 - 16 (1 bit)
access : read-write

CUTRGF2 : ADC Trigger Flag by Counting Up to CMP\nNote: Software can write 1 to clear this bit.
bits : 18 - 18 (1 bit)
access : read-write

CDTRGF3 : ADC Trigger Flag by Counting Down to CMP\nNote: Software can write 1 to clear this bit.
bits : 24 - 24 (1 bit)
access : read-write

CUTRGF3 : ADC Trigger Flag by Counting Up to CMP\nNote: Software can write 1 to clear this bit.
bits : 26 - 26 (1 bit)
access : read-write

PWM0MD : Enable PWM0 Mask Data\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM1MD : Enable PWM1 Mask Data\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM2MD : Enable PWM2 Mask Data\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM3MD : Enable PWM3 Mask Data\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM4MD : Enable PWM4 Mask Data\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM5MD : Enable PWM5 Mask Data\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM0ME : Enable PWM0 Mask Function\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM1ME : Enable PWM1 Mask Function\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM2ME : Enable PWM2 Mask Function\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM3ME : Enable PWM3 Mask Function\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM4ME : Enable PWM4 Mask Function\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM5ME : Enable PWM5 Mask Function\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGSEL : Phase Change Trigger Selection\nSelect the trigger condition to load PHCHG from PHCHG_NXT.\nWhen the trigger condition occurs it will load PHCHG_NOW with PHCHG_NXT.\nPhase Change: PWM outputs are masked according with\n the definition of PWMx_ME and PWMx_MD in PHCHG_NOW.\n
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMP0SEL : Alternative Comparator 0 Positive Input Selection\nSelect the positive input source of ACMP0.\n
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMP1SEL : Alternative Comparator 1 Positive Input Selection\nSelect the positive input source of ACMP1.\n
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMP0ST : Start CMP0 Compare Function\n
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMP1ST : Start CMP1 Compare Function\n
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PHCHGEN : Enable Auto Phase Change Function\n
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM0MD : Enable PWM0 Mask Data Preset Bit\nThis bit will be load to bit PWM0_MD in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
bits : 0 - 0 (1 bit)
access : read-write

PWM1MD : Enable PWM1 Mask Data Preset Bit\nThis bit will be load to bit PWM1_MD in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
bits : 1 - 1 (1 bit)
access : read-write

PWM2MD : Enable PWM2 Mask Data Preset Bit\nThis bit will be load to bit PWM2_MD in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
bits : 2 - 2 (1 bit)
access : read-write

PWM3MD : Enable PWM3 Mask Data Preset Bit\nThis bit will be load to bit PWM3_MD in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
bits : 3 - 3 (1 bit)
access : read-write

PWM4MD : Enable PWM4 Mask Data Preset Bit\nThis bit will be load to bit PWM4_MD in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
bits : 4 - 4 (1 bit)
access : read-write

PWM5MD : Enable PWM5 Mask Data Preset Bit\nThis bit will be load to bit PWM5_MD in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
bits : 5 - 5 (1 bit)
access : read-write

PWM0ME : Enable PWM0 Mask Function Preset Bit\nThis bit will be load to bit PWM0_ME in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
bits : 8 - 8 (1 bit)
access : read-write

PWM1ME : Enable PWM1 Mask Function Preset Bit\nThis bit will be load to bit PWM1_ME in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
bits : 9 - 9 (1 bit)
access : read-write

PWM2ME : Enable PWM2 Mask Function Preset Bit\nThis bit will be load to bit PWM2_ME in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
bits : 10 - 10 (1 bit)
access : read-write

PWM3ME : Enable PWM3 Mask Function Preset Bit\nThis bit will be load to bit PWM3_ME in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
bits : 11 - 11 (1 bit)
access : read-write

PWM4ME : Enable PWM4 Mask Function Preset Bit\nThis bit will be load to bit PWM4_ME in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
bits : 12 - 12 (1 bit)
access : read-write

PWM5ME : Enable PWM5 Mask Function Preset Bit\nThis bit will be load to bit PWM5_ME in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
bits : 13 - 13 (1 bit)
access : read-write

HALLSTS : Predicted Next HALL State\nThis bit field indicates the predicted hall state at next commutation. \nthe hardware will compare bits (CAP2, CAP1, CAP0) in timer 2 with HALL_STATE[2:0] when any hall state change occurs.\n If the comparison is matched it will trigger phase change function.
bits : 16 - 18 (3 bit)
access : read-write

TRGSEL : Phase Change Trigger Selection Preset Bits\nThis bit field will be load to bit field TRGSEL in PHCHG_NOW when load trigger condition occurs.\nRefer to register PWM_PHCHG for detailed definition.
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMP0SEL : Alternative Comparator 0 Positive Input Selection Preset Bits\nThis bit field will be load to bit field CMP0SEL in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
bits : 24 - 25 (2 bit)
access : read-write

CMP1SEL : Alternative Comparator 1 Positive Input Selection Preset Bitfs\nThis bit field will be load to bit field CMP1SEL in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
bits : 26 - 27 (2 bit)
access : read-write

CMP0ST : Start CMP0 Compare Function Control Preset Bit\nThis bit will be load to bit CMP0_ST in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
bits : 28 - 28 (1 bit)
access : read-write

CMP1ST : Start CMP1 Compare Function Control Preset Bit\nThis bit will be load to bit CMP1_ST in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
bits : 29 - 29 (1 bit)
access : read-write

PHCHGEN : Enable Auto Phase Change Function Preset Bit\nThis bit will be load to bit PHCHG_EN in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
bits : 31 - 31 (1 bit)
access : read-write

CNTEN0 : PWM-timer 0 Enable/Disable Start Run\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN1 : PWM-timer 1 Enable/Disable Start Run\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN2 : PWM-timer 2 Enable/Disable Start Run\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN3 : PWM-timer 3 Enable/Disable Start Run\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN4 : PWM-timer 4 Enable/Disable Start Run\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN5 : PWM-timer 5 Enable/Disable Start Run\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTMODE : PWM-timer Auto-reload/One-shot Mode\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HCUPDT : Half Cycle Update Enable for Center-aligned Type\n
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ASYMEN : Asymmetric Mode in Center-aligned Type
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBGTRIOFF : PWM Debug Mode Configuration Bit (Available in DEBUG Mode Only)\n
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DTCNT01 : Dead-zone 0 Generator Enable/Disable (PWM0 and PWM1 Pair for PWM Group)\nNote: When the dead-zone generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DTCNT23 : Dead-zone 2 Generator Enable/Disable (PWM2 and PWM3 Pair for PWM Group)\nNote: When the dead-zone generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DTCNT45 : Dead-zone 4 Generator Enable/Disable (PWM4 and PWM5 Pair for PWM Group)\nNote: When the dead-zone generator is enabled, the pair of PWM4 and PWM5 becomes a complementary pair for PWM group.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTCLR : Clear PWM Counter Control Bit\nNote: It is automatically cleared by hardware.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE : PWM Operating Mode Selection\n
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GROUPEN : Group Bit\n
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTTYPE : PWM Aligned Type Selection Bit\n
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMP0ALT : Alternative CMP0 Positive Input Source Select\nNote: Register CMP0CR is describe in Comparator Controller chapter
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMP1ALT : Alternative CMP1 Positive Input Source Select\nNote: Register CMP1CR is describe in Comparator Controller chapter
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IFAEN : Enable Period Interrupt Accumulation Function\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IFACNTVAL : Period Interrupt Accumulation Counter Value Setting Register (Write Only)\n16 step Down-Counter value setting register.\nWhen IFAEN is set, IFACNTVAL value will load into IFACNTDAT and decrase gradually.
bits : 4 - 7 (4 bit)
access : write-only

IFACNTDAT : Period Interrupt Down-counter Data Register (Read Only)\nWhen IFAEN is set, IFACNTDAT will decrease when every PWM Interrupt flag is set,\n and when IFACNTDAT reach to zero, the PWM interrupt will occurred and IFACNTVAL will reload to IFACNTDAT.
bits : 12 - 15 (4 bit)
access : read-only

PERIOD : PWM Counter/Timer Loaded Value PERIODn determines the PWM Period. Edge-aligned mode: where xy, could be 01, 23, 45 depending on the selected PWM channel. Note: Any write to PERIODn will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write