BPWM_CLKPSC (CLKPSC)

BPWM_CMPDAT0 (CMPDAT0)

BPWM_DAT0 (DAT0)

BPWM_PERIOD1 (PERIOD1)

BPWM_CMPDAT1 (CMPDAT1)

BPWM_DAT1 (DAT1)

BPWM_CLKDIV (CLKDIV)

BPWM_INTEN (INTEN)

BPWM_INTSTS (INTSTS)

BPWM_CAPCTL (CAPCTL)

BPWM_CAPDRL0 (CAPDRL0)

BPWM_CAPDFL0 (CAPDFL0)

BPWM_CAPDRL1 (CAPDRL1)

BPWM_CAPDFL1 (CAPDFL1)

BPWM_CAPEN (CAPEN)

BPWM_POEN (POEN)

BPWM_CTL (CTL)

BPWM_PERIOD0 (PERIOD0)

CP01 : Clock Prescaler\nClock input is divided by (CP01 + 1) before it is fed to the corresponding PWM-timer\n
bits : 0 - 7 (8 bit)
access : read-write

DZI01 : Dead-zone Interval for Pair of Channel 0 and Channel 1\nThese 8-bit determine the Dead-zone length.\n
bits : 16 - 23 (8 bit)
access : read-write

CMP : PWM Comparator Register\nCMP determines the PWM duty.\nNote: Any write to PERIOD will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write

PDR : PWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter.
bits : 0 - 15 (16 bit)
access : read-only

CLKDIV0 : PWM Timer 0 Clock Source Divider Selection\nSelect clock source divider for PWM timer 0.\n(Table is the same as CLKDIV1)
bits : 0 - 2 (3 bit)
access : read-write

CLKDIV1 : PWM Timer 1 Clock Source Divider Selection\nSelect clock source divider for PWM timer 1.\n
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BPWMPIE0 : BPWM Channel 0 Period Interrupt Enable Bit \n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BPWMPIE1 : BPWM Channel 1 Period Interrupt Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BPWMDIE0 : BPWM Channel 0 Duty Interrupt Enable Bit\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BPWMDIE1 : BPWM Channel 1 Duty Interrupt Enable Bit\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTTYPE : BPWM Interrupt Period Type Selection Bit\nNote: This bit is effective when BPWM in Center-aligned type only.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BPWMPIF0 : BPWM Channel 0 Period Interrupt Status\nThis bit is set by hardware when BPWM0 counter reaches the requirement of interrupt (depend on INTTYPE bit of PWM_INTEN register), software can write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write

BPWMPIF1 : BPWM Channel 1 Period Interrupt Status\nThis bit is set by hardware when BPWM1 counter reaches the requirement of interrupt (depend on INTTYPE bit of PWM_INTEN register), software can write 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write

BPWMDIF0 : BPWM Channel 0 Duty Interrupt Flag\nFlag is set by hardware when channel 0 BPWM counter down count and reaches CMP0, software can clear this bit by writing a one to it.\nNote: If CMP equal to PERIOD, this flag is not working in Edge-aligned type selection
bits : 8 - 8 (1 bit)
access : read-write

BPWMDIF1 : BPWM Channel 1 Duty Interrupt Flag\nFlag is set by hardware when channel 1 BPWM counter down count and reaches CMP1, software can clear this bit by writing a one to it.\nNote: If CMP equal to PERIOD, this flag is not working in Edge-aligned type selection
bits : 9 - 9 (1 bit)
access : read-write

INV0 : Channel 0 Inverter Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRL_IE0 : Channel 0 Rising Latch Interrupt Enable Bit\nWhen Enabled, if Capture detects BPWM channel 0 has rising transition, Capture will issue an Interrupt.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFL_IE0 : Channel 0 Falling Latch Interrupt Enable BIt\nWhen Enabled, if Capture detects BPWM channel 0 has falling transition, Capture will issue an Interrupt.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPCH0EN : Channel 0 Capture Function Enable Bit\nWhen Enabled, Capture latched the BPWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable BPWM channel 0 Interrupt.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPIF0 : Channel 0 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write

CRLRI0 : BPWM_CAPDRL0Latched Indicator Bit\nWhen BPWM input channel 0 has a rising transition, BPWM_CAPDRL0 was latched with the value of BPWM down-counter and this bit is set by hardware.\nSoftware can write 1 to clear this bit to 0.
bits : 6 - 6 (1 bit)
access : read-write

CFLRI0 : BPWM_CAPDRL0 Latched Indicator Bit\nWhen BPWM input channel 0 has a falling transition, BPWM_CAPDRL0 was latched with the value of BPWM down-counter and this bit is set by hardware.\nSoftware can write 1 to clear this bit to0.
bits : 7 - 7 (1 bit)
access : read-write

INV1 : Channel 1 Inverter Enable Bit\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRL_IE1 : Channel 1 Rising Latch Interrupt Enable Bit\nWhen Enabled, if Capture detects BPWM channel 1 has rising transition, Capture will issue an Interrupt.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFL_IE1 : Channel 1 Falling Latch Interrupt Enable\nWhen Enabled, if Capture detects BPWM channel 1 has falling transition, Capture will issue an Interrupt.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPCH1EN : Channel 1 Capture Function Enable Bit\nWhen Enabled, Capture latched the BPWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM channel 1 Interrupt.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPIF1 : Channel 1 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0.
bits : 20 - 20 (1 bit)
access : read-write

CRLRI1 : CRLR1 Latched Indicator Bit\nWhen BPWM input channel 1 has a rising transition, CRLR1 was latched with the value of BPWM down-counter and this bit is set by hardware.\nSoftware can write 1 to clear this bit to0.
bits : 22 - 22 (1 bit)
access : read-write

CFLRI1 : CFLR1 Latched Indicator Bit\nWhen BPWM input channel 1 has a falling transition, CFLR1 was latched with the value of BPWM down-counter and this bit is set by hardware.\nSoftware can write 1 to clear this bit to 0
bits : 23 - 23 (1 bit)
access : read-write

CRLR : Capture Rising Latch Register\nLatch the BPWM counter when Channel 0/1 has rising transition.
bits : 0 - 15 (16 bit)
access : read-only

CFLR : Capture Falling Latch Register\nLatch the BPWM counter when Channel 0/1 has Falling transition.
bits : 0 - 15 (16 bit)
access : read-only

CINEN0 : Channel 0 Capture Input Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CINEN1 : Channel 1 Capture Input Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POE0 : Channel 0 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to BPWM function
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POE1 : Channel 1 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to BPWM function
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH0EN : PWM-timer 0 Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH0PINV : PWM-timer 0 Output Polar Inverse Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH0INV : PWM-timer 0 Output Inverter Enable Bit\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH0MOD : PWM-timer 0 Auto-reload/One-shot Mode\nNote: If there is a transition at this bit, it will cause PWM_PERIOD0 and CMP0 be cleared.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DZEN01 : Dead-zone 0 Generator Enable Bit\nNote: When Dead-zone generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH1EN : PWM-timer 1 Enable Bit\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH1PINV : PWM-timer 1 Output Polar Inverse Enable Bit\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH1INV : PWM-timer 1 Output Inverter Enable\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH1MOD : PWM-timer 1 Auto-reload/One-shot Mode\nNote: If there is a transition at this bit, it will cause PERIOD1 and CMP1 be cleared.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM01TYPE : PWM01 Aligned Type Selection Bit \n
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PERIOD : Basic PWM Period Counter Register\nPERIOD data determines the PWM period.\nNote: Any write to PERIOD will take effect in next PWM cycle.\nNote: When PWM operating at Center-aligned type, PERIOD value should be set between 0x0000 to 0xFFFE. If PERIOD equal to 0xFFFF, the PWM will work unpredictable.\nNote: When PERIOD value is set to 0, PWM output is always high.
bits : 0 - 15 (16 bit)
access : read-write