\n
address_offset : 0x0 Bytes (0x0)
size : 0x88 byte (0x0)
mem_usage : registers
protection : not protected
IRQ0 (BOD) interrupt source identity
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit0 : BOD_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ4 (P0/1) interrupt source identity
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit1: P1_INT\nBit0: P0_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ5 (P2/3/4) interrupt source identity
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: P4_INT\nBit1: P3_INT\nBit0: P2_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ6 (PWMA) interrupt source identity
address_offset : 0x18 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit3: PWM3_INT\nBit2: PWM2_INT\nBit1: PWM1_INT\nBit0: PWM0_INT
bits : 0 - 3 (4 bit)
access : read-only
IRQ7 (PWMB) interrupt source identity
address_offset : 0x1C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit3: PWM7_INT\nBit2: PWM6_INT\nBit1: PWM5_INT\nBit0: PWM4_INT
bits : 0 - 3 (4 bit)
access : read-only
IRQ8 (TMR0) interrupt source identity
address_offset : 0x20 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit0: TMR0_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ9 (TMR1) interrupt source identity
address_offset : 0x24 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit0: TMR1_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ10 (TMR2) interrupt source identity
address_offset : 0x28 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit0: TMR2_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ11 (TMR3) interrupt source identity
address_offset : 0x2C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit0: TMR3_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ12 (UART0) interrupt source identity
address_offset : 0x30 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit0: UART0_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ13 (UART1) interrupt source identity
address_offset : 0x34 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit0: UART1_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ14 (SPI0) interrupt source identity
address_offset : 0x38 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit0: SPI0_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ15 (SPI1) interrupt source identity
address_offset : 0x3C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit0: SPI1_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ1 (WDT) interrupt source identity
address_offset : 0x4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit0 : WDT_INT
bits : 0 - 2 (3 bit)
access : read-only
Reserved
address_offset : 0x40 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Reserved
address_offset : 0x44 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ18 (I2C0) interrupt source identity
address_offset : 0x48 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit0: I2C0_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ19 (I2C1) interrupt source identity
address_offset : 0x4C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit0: I2C1_INT
bits : 0 - 2 (3 bit)
access : read-only
Reserved
address_offset : 0x50 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Reserved
address_offset : 0x54 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Reserved
address_offset : 0x58 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Reserved
address_offset : 0x5C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Reserved
address_offset : 0x60 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ25 (ACMPA) interrupt source identity
address_offset : 0x64 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit0: ACMPA_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ26 (ACMPB) interrupt source identity
address_offset : 0x68 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit0: ACMPB_INT
bits : 0 - 2 (3 bit)
access : read-only
Reserved
address_offset : 0x6C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ28 (PWRWU) interrupt source identity
address_offset : 0x70 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit0: PWRWU_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ29 (ADC) interrupt source identity
address_offset : 0x74 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit0: ADC_INT
bits : 0 - 2 (3 bit)
access : read-only
Reserved
address_offset : 0x78 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Reserved
address_offset : 0x7C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ2 (EINT0) interrupt source identity
address_offset : 0x8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit0: EINT0 - external interrupt 0 from P3.2
bits : 0 - 2 (3 bit)
access : read-only
NMI source interrupt select control register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NMI_SEL : NMI interrupt source selection\nThe NMI interrupt to Cortex-M0 can be selected from one of the interrupt[31:0]\nThe NMI_SEL bit[4:0] used to select the NMI interrupt source
bits : 0 - 4 (5 bit)
access : read-write
NMI_EN : NMI interrupt enable (write-protection bit)
This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable NMI interrupt
#1 : 1
Enable NMI interrupt
End of enumeration elements list.
MCU Interrupt Request Source Register
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_IRQ : MCU IRQ Source Register
The MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0 core. There are two modes to generate interrupt to Cortex-M0, the normal mode and test mode.
The MCU_IRQ collects all interrupts from each peripheral and synchronizes them then interrupts the Cortex-M0.
When the MCU_IRQ[n] is 0 , set MCU_IRQ[n] 1 will generate an interrupt to Cortex_M0 NVIC[n].
When the MCU_IRQ[n] is 1 (mean an interrupt is assert), set 1 to the MCU_IRQ[n] will clear the interrupt and set MCU_IRQ[n] 0 : no any effect
bits : 0 - 31 (32 bit)
access : read-write
IRQ3 (EINT1) interrupt source identity
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit0: EINT1 - external interrupt 1 from P3.3
bits : 0 - 2 (3 bit)
access : read-only
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