Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected
System Power Down Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XTL12M_EN : External Crystal Oscillator enable (write-protected)
The bit default value is set by flash controller user configuration register config0 [26:24]. When the default clock source is from external crystal, the bit is automatically set to 1
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Crystal oscillation disable
#1 : 1
Crystal oscillation enable
End of enumeration elements list.
OSC22M_EN : Internal 22.1184 MHz Oscillator enable (write-protected)
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
22.1184 MHz Oscillation disable
#1 : 1
22.1184 MHz Oscillation enable
End of enumeration elements list.
OSC10K_EN : Internal 10 kHz Oscillator enable (write-protected)
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
10 kHz Oscillation disable
#1 : 1
10 kHz Oscillation enable
End of enumeration elements list.
PD_WU_DLY : Enable the wake up delay counter. (write-protected)
When the chip wakes up from power down mode, the clock control will delay certain clock cycles to wait system clock stable.
The delayed clock cycle is 4096 clock cycles when chip work at external crystal (4 ~ 24MHz), and 256 clock cycles when chip work at 22.1184 MHz oscillator.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable clock cycles delay
#1 : 1
Enable clock cycles delay
End of enumeration elements list.
PD_WU_INT_EN : Power down mode wake Up Interrupt Enable (write-protected)\nThe interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
PD_WU_STS : Power down mode wake up interrupt status
Set by power down wake up event , it indicates that resume from power down mode
The flag is set if the GPIO, UART, WDT, ACMPA, ACMPB , I2C, TIMER, or BOD wakeup occurred
Write 1 to clear the bit to zero.
Note: This bit is working only if PD_WU_INT_EN (PWRCON[5]) set to 1.
bits : 6 - 6 (1 bit)
access : read-write
PWR_DOWN_EN : System power down enable bit (write-protected)
When CPU sets this bit 1 the chip power down mode is enabled, and chip power-down behavior will depends on the PD_WAIT_CPU bit
(a) If the PD_WAIT_CPU is 0 , then the chip enters power down mode immediately after the PWR_DOWN_EN bit set.
(b) if the PD_WAIT_CPU is 1 , then the chip keeps active till the CPU sleep mode is also active and then the chip enters power down mode
When chip wakes up from power down mode, this bit is auto cleared. Users need to set this bit again for next power down.
When in power down mode, external crystal (4~ 24MHz) and the 22.1184 MHz OSC will be disabled in this mode, but the 10 kHz OSC is not controlled by power down mode.
When in power down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by power down mode, if the peripheral clock source is from 10 kHz oscillator.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip operate in normal mode or CPU in idle mode (sleep mode) because of WFI command
#1 : 1
Chip enter the power down mode instant or wait CPU sleep command WFI
End of enumeration elements list.
PD_WAIT_CPU : This bit control the power down entry condition (write-protected)
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip entry power down mode when the PWR_DOWN_EN bit is set to 1
#1 : 1
Chip enter power down mode when the both PWR_DOWN_EN bit is set to 1 and CPU run WFI instruction
End of enumeration elements list.
Clock Source Select Control Register 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLK_S : HCLK Clock Source Select (Write-protection Bits)
Before clock switching, the related clock sources (both pre-select and new-select) must be turn on
The 3-bit default value is reloaded from the value of CFOSC (CONFIG [26:24]) in user configuration register of Flash controller by any reset. Therefore the default value is either 000b or 111b.
These bits are protected bit. It means programming them needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external 4~24 MHz high speed crystal oscillator clock
#001 : 1
reserved
#010 : 2
Clock source from PLL clock
#011 : 3
Clock source from internal 10 kHz low speed oscillator clock
#111 : 7
Clock source from internal 22.1184 MHz high speed oscillator clock
End of enumeration elements list.
STCLK_S : Cortex-M0 SysTick Clock Source Select (write-protected)
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external 4~24 MHz high speed crystal clock
#001 : 1
reserved
#010 : 2
Clock source from external 4~24 MHz high speed crystal clock/2
#011 : 3
Clock source from HCLK/2
#111 : 7
Clock source from internal 22.1184 MHz high speed oscillator clock/2
End of enumeration elements list.
Clock Source Select Control Register 1
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_S : WDT clock source select (write-protected)
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Reserved
#01 : 1
Reserved
#10 : 2
Clock source from HCLK/2048 clock
#11 : 3
Clock source from internal 10 kHz oscillator clock
End of enumeration elements list.
ADC_S : ADC clock source select
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from external crystal clock (4 ~ 24MHz)
#01 : 1
Clock source from PLL clock
#10 : 2
Clock source from HCLK
#11 : 3
Clock source from internal 22.1184 MHz oscillator clock
End of enumeration elements list.
SPI0_S : SPI0 clock source select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source from PLL clock
#1 : 1
Clock source from HCLK
End of enumeration elements list.
SPI1_S : SPI1 clock source select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source from PLL clock
#1 : 1
Clock source from HCLK
End of enumeration elements list.
TMR0_S : TIMER0 clock source select.
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external crystal clock (4 ~ 24 MHz)
#010 : 2
Clock source from HCLK
#011 : 3
Clock source from external trigger T0
#101 : 5
Clock source from internal 10 kHz low speed oscillator clock
#111 : 7
Clock source from internal 22.1184 MHz oscillator clock
End of enumeration elements list.
TMR1_S : TIMER1 clock source select.
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external crystal clock (4 ~ 24MHz)
#010 : 2
Clock source from HCLK
#011 : 3
Clock source from external trigger T1
#101 : 5
Clock source from internal 10 kHz low speed oscillator clock
#111 : 7
Clock source from internal 22.1184 MHz oscillator clock
End of enumeration elements list.
TMR2_S : TIMER2 clock source select.
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external crystal clock (4 ~ 24MHz)
#010 : 2
Clock source from HCLK
#011 : 3
Clock source from external trigger T2
#101 : 5
Clock source from internal 10 kHz low speed oscillator clock
#111 : 7
Clock source from internal 22.1184 MHz oscillator clock
End of enumeration elements list.
TMR3_S : TIMER3 clock source select.
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external crystal clock (4 ~ 24MHz)
#010 : 2
Clock source from HCLK
#011 : 3
Clock source from external trigger T3
#101 : 5
Clock source from internal 10 kHz low speed oscillator clock
#111 : 7
Clock source from internal 22.1184 MHz oscillator clock
End of enumeration elements list.
UART_S : UART clock source select.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from external crystal clock (4 ~ 24MHz)
#01 : 1
Clock source from PLL clock
#10 : 2
Reserved
#11 : 3
Clock source from internal 22.1184 MHz oscillator clock
End of enumeration elements list.
PWM01_S : PWM0 and PWM1 clock source select.\nPWM0 and PWM1 uses the same Engine clock source, both of them use the same pre-scalar
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from external crystal clock ( 4 ~ 24MHz)
#01 : 1
Clock source from internal 10 kHz low speed oscillator clock
#10 : 2
Clock source from HCLK
#11 : 3
Clock source from internal 22.1184 MHz oscillator clock
End of enumeration elements list.
PWM23_S : PWM2 and PWM3 clock source select.\nPWM2 and PWM3 uses the same Engine clock source, both of them use the same pre-scalar
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from external crystal clock (4 ~ 24MHz)
#01 : 1
Clock source from internal 10 kHz low speed oscillator clock
#10 : 2
Clock source from HCLK
#11 : 3
Clock source from internal 22.1184 MHz oscillator clock
End of enumeration elements list.
Clock Divider Number Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLK_N : HCLK clock divide number from HCLK clock source
bits : 0 - 3 (4 bit)
access : read-write
UART_N : UART clock divide number from UART clock source
bits : 8 - 11 (4 bit)
access : read-write
ADC_N : ADC clock divide number from ADC clock source
bits : 16 - 23 (8 bit)
access : read-write
Clock Source Select Control Register 2
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRQDIV_S : Clock Divider Clock Source Select
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from external crystal clock (4 ~ 24 MHz)
#01 : 1
Reserved
#10 : 2
Clock source from HCLK
#11 : 3
Clock source from internal 22.1184 MHz oscillator clock
End of enumeration elements list.
PWM45_S : PWM4 and PWM5 clock source select\nPWM4 and PWM5 used the same Engine clock source, both of them use the same pre-scalar
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from external crystal clock (4 ~ 24 MHz)
#01 : 1
Clock source from internal 10 kHz low speed oscillator clock
#10 : 2
Clock source from HCLK
#11 : 3
Clock source from internal 22.1184 MHz oscillator clock
End of enumeration elements list.
PWM67_S : PWM6 and PWM7 clock source select\nPWM6 and PWM7 used the same Engine clock source, both of them use the same pre-scalar
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from external crystal clock (4 ~ 24MHz)
#01 : 1
Clock source from internal 10 kHz low speed oscillator clock
#10 : 2
Clock source from HCLK
#11 : 3
Clock source from internal 22.1184 MHz oscillator clock
End of enumeration elements list.
WWDT_S : Window Watchdog Timer clock source select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#10 : 2
Clock source from HCLK/2048 clock
#11 : 3
Clock source from internal 10 kHz low speed oscillator clock
End of enumeration elements list.
PLL Control Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FB_DV : PLL Feedback Divider Control
bits : 0 - 8 (9 bit)
access : read-write
IN_DV : PLL Input Divider Control
bits : 9 - 13 (5 bit)
access : read-write
OUT_DV : PLL Output Divider Control
bits : 14 - 15 (2 bit)
access : read-write
PD : Power down Mode\nIf the PWR_DOWN_EN bit is set to 1 in PWRCON register, the PLL will enter Power-down mode too.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL is in Normal mode
#1 : 1
PLL is in Power-down mode (default)
End of enumeration elements list.
BP : PLL Bypass Control
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL is in Normal mode (default)
#1 : 1
PLL clock output is same as PLL source clock input
End of enumeration elements list.
OE : PLL OE (FOUT enable) pin Control
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL FOUT enable
#1 : 1
PLL FOUT is fixed low
End of enumeration elements list.
PLL_SRC : PLL Source Clock Select
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL source clock from external crystal (4 ~ 24 MHz)
#1 : 1
PLL source clock from 22.1184 MHz oscillator
End of enumeration elements list.
Frequency Divider Control Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSEL : Divider Output Frequency Selection Bits\nThe formula of output frequency is\nFin is the input clock frequency\nFout is the frequency of divider output clock\nN is the 4-bit value of FSEL[3:0].
bits : 0 - 3 (4 bit)
access : read-write
DIVIDER_EN : Frequency Divider Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable Frequency Divider
#1 : 1
Enable Frequency Divider
End of enumeration elements list.
AHB Devices Clock Enable Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISP_EN : Flash ISP Controller Clock Enable Control.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
To disable the Flash ISP controller clock
#1 : 1
To enable the Flash ISP controller clock
End of enumeration elements list.
EBI_EN : EBI Controller Clock Enable Control.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the EBI controller clock
#1 : 1
Enable the EBI controller clock
End of enumeration elements list.
DIV_EN : Hardware Divider Controller Clock Enable Control
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Hardware Divider engine clock Disabled
#1 : 1
Hardware Divider engine clock Enabled
End of enumeration elements list.
APB Devices Clock Enable Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_EN : Watchdog Timer Clock Enable (write-protected)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable Watchdog Timer Clock
#1 : 1
Enable Watchdog Timer Clock
End of enumeration elements list.
TMR0_EN : Timer0 Clock Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable Timer0 Clock
#1 : 1
Enable Timer0 Clock
End of enumeration elements list.
TMR1_EN : Timer1 Clock Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable Timer1 Clock
#1 : 1
Enable Timer1 Clock
End of enumeration elements list.
TMR2_EN : Timer2 Clock Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable Timer2 Clock
#1 : 1
Enable Timer2 Clock
End of enumeration elements list.
TMR3_EN : Timer3 Clock Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable Timer3 Clock
#1 : 1
Enable Timer3 Clock
End of enumeration elements list.
FDIV_EN : Clock Divider Clock Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable FDIV Clock
#1 : 1
Enable FDIV Clock
End of enumeration elements list.
I2C_EN : I2C0 Clock Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable I2C0 Clock
#1 : 1
Enable I2C0 Clock
End of enumeration elements list.
I2C1_EN : I2C1 Clock Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable I2C1 Clock
#1 : 1
Enable I2C1 Clock
End of enumeration elements list.
SPI0_EN : SPI0 Clock Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable SPI0 Clock
#1 : 1
Enable SPI0 Clock
End of enumeration elements list.
SPI1_EN : SPI1 Clock Enable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable SPI1 Clock
#1 : 1
Enable SPI1 Clock
End of enumeration elements list.
UART0_EN : UART0 Clock Enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable UART0 clock
#1 : 1
Enable UART0 clock
End of enumeration elements list.
UART1_EN : UART1 Clock Enable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable UART1 clock
#1 : 1
Enable UART1 clock
End of enumeration elements list.
PWM01_EN : PWM_01 Clock Enable
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable PWM01 clock
#1 : 1
Enable PWM01 clock
End of enumeration elements list.
PWM23_EN : PWM_23 Clock Enable
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable PWM23 clock
#1 : 1
Enable PWM23 clock
End of enumeration elements list.
PWM45_EN : PWM_45 Clock Enable
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable PWM45 clock
#1 : 1
Enable PWM45 clock
End of enumeration elements list.
PWM67_EN : PWM_67 Clock Enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable PWM67 clock
#1 : 1
Enable PWM67 clock
End of enumeration elements list.
ADC_EN : Analog-Digital-Converter (ADC) Clock Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable ADC clock
#1 : 1
Enable ADC clock
End of enumeration elements list.
ACMPA_EN : Analog Comparator A Clock Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the Analog Comparator A Clock
#1 : 1
Enable the Analog Comparator A Clock
End of enumeration elements list.
ACMPB_EN : Analog Comparator B Clock Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the Analog Comparator B Clock
#1 : 1
Enable the Analog Comparator B Clock
End of enumeration elements list.
Clock status monitor Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XTL12M_STB : External Crystal clock source stable flag (Read Only)
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
External Crystal clock is not stable or disable
#1 : 1
External Crystal clock is stable
End of enumeration elements list.
PLL_STB : PLL clock source stable flag (Read Only)
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
PLL clock is not stable or disable
#1 : 1
PLL clock is stable
End of enumeration elements list.
OSC10K_STB : OSC10K clock source stable flag (Read Only)
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
OSC10K clock is not stable or disable
#1 : 1
OSC10K clock is stable
End of enumeration elements list.
OSC22M_STB : OSC22M (Internal 22.1184 MHz) clock source stable flag (Read Only)
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
OSC22M clock is not stable or disable
#1 : 1
OSC22M clock is stable
End of enumeration elements list.
CLK_SW_FAIL : Clock Switching Fail Flag\nThis bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.\nWrite 1 to clear the bit to 0.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock switching success
#1 : 1
Clock switching failed
End of enumeration elements list.
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