SPI_CNTRL

SPI_RX0

SPI_TX0

SPI_CNTRL2

SPI_DIVIDER

SPI_FIFO_CTL

SPI_STATUS

SPI_SSR

GO_BUSY : SPI Transfer Control Bit and Busy Status\nIf the FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically.\nIn FIFO mode, this bit will be controlled by hardware. Software should not modify this bit.\nNote:\nAll registers should be set before writing 1 to this GO_BUSY bit.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

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RX_NEG : Receive on Negative Edge
bits : 1 - 1 (1 bit)
access : read-write

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TX_NEG : Transmit on Negative Edge
bits : 2 - 2 (1 bit)
access : read-write

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TX_BIT_LEN : Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.
bits : 3 - 7 (5 bit)
access : read-write

LSB : LSB First
bits : 10 - 10 (1 bit)
access : read-write

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CLKP : Clock Polarity
bits : 11 - 11 (1 bit)
access : read-write

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SP_CYCLE : Suspend Interval (Master Only)\nThese four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation:\n(SP_CYCLE[3:0] + 0.5) * period of SPICLK clock cycle\nExample:
bits : 12 - 15 (4 bit)
access : read-write

IF : SPI Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
bits : 16 - 16 (1 bit)
access : read-write

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IE : SPI Unit Transfer Interrupt Enable Bit
bits : 17 - 17 (1 bit)
access : read-write

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SLAVE : Slave Mode Enable Bit
bits : 18 - 18 (1 bit)
access : read-write

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REORDER : Byte Reorder Function\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.
bits : 19 - 19 (1 bit)
access : read-write

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FIFO : FIFO Mode Note: Before enabling FIFO mode, the other related settings should be set in advance. In master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after writing data into the 8-depth FIFO. It means all data stored at transmit FIFO buffer are transferred when the transmit FIFO buffer is empty and the GO_BUSY bit back to 0.
bits : 21 - 21 (1 bit)
access : read-write

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RX_EMPTY : Receive FIFO Buffer Empty Indicator (read only)\nIt's a mutual mirror bit of SPI_CNTRL[24].
bits : 24 - 24 (1 bit)
access : read-only

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RX_FULL : Receive FIFO Buffer Full Indicator (read only)\nIt's a mutual mirror bit of SPI_STATUS[25].
bits : 25 - 25 (1 bit)
access : read-only

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TX_EMPTY : Transmit FIFO Buffer Empty Indicator (read only)\nIt's a mutual mirror bit of SPI_STAUTS[26].
bits : 26 - 26 (1 bit)
access : read-only

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TX_FULL : Transmit FIFO Buffer Full Indicator (read only)\nIt's a mutual mirror bit of SPI_STATUS[27].
bits : 27 - 27 (1 bit)
access : read-only

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RX : Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If the FIFO mode is disabled, the software can access the last received data by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit, SPI_CNTRL[24] or SPI_STATUS[24], is not set to 1, the software can access the receive FIFO buffer by reading this register. This is a read-only register.
bits : 0 - 31 (32 bit)
access : read-only

TX : Data Transmit Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bit TX[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: when the SPI controller is configured as a slave device and the FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the software must update the transmit data register before setting the GO_BUSY bit to 1.
bits : 0 - 31 (32 bit)
access : write-only

NOSLVSEL : Slave 3-Wire Mode Enable Bit\nThis is used to ignore the slave select signal in slave mode. The SPI controller can work with 3-wire interface including SPICLK, SPI_MISO, and SPI_MOSI.\nNote: In 3-wire mode, the SS_LTRIG, SPI_SSR[4], shall be set as 1.
bits : 8 - 8 (1 bit)
access : read-write

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SLV_ABORT : Slave 3-Wire Mode Abort Control Bit\nIn normal operation, there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more serial clock input over the one transfer time in slave 3-wire mode, the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event. \nNote: It will be cleared to 0 automatically by hardware after the software sets this bit to 1.
bits : 9 - 9 (1 bit)
access : read-write

SSTA_INTEN : Slave 3-Wire Mode Start Interrupt Enable\nIt is used to enable interrupt when the transfer has started in slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done.
bits : 10 - 10 (1 bit)
access : read-write

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SLV_START_INTSTS : Slave 3-Wire Mode Start Interrupt Status\nIt is used to dedicate that the transfer has started in slave 3-wire mode.
bits : 11 - 11 (1 bit)
access : read-write

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SS_INT_OPT : Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.
bits : 16 - 16 (1 bit)
access : read-write

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BCn : SPI Engine Clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details.
bits : 31 - 31 (1 bit)
access : read-write

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DIVIDER : Clock Divider Register (master only)\nThe value in this field is the frequency divider for generating the SPI engine clock and its SPI clock. The frequency is obtained according to the following equation:\nIf the bit of BCn, SPI_CNTRL2[31], is set to'0'.\n\nelse if BCn is set to '1',\n\nwhere \n is the SPI engine clock source. It is defined in the CLKSEL1 register.
bits : 0 - 7 (8 bit)
access : read-write

RX_CLR : Clear Receive FIFO Buffer
bits : 0 - 0 (1 bit)
access : read-write

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TX_CLR : Clear Transmit FIFO Buffer
bits : 1 - 1 (1 bit)
access : read-write

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RX_INTEN : Receive Threshold Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

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TX_INTEN : Transmit Threshold Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

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RXOV_INTEN : Receive FIFO Overrun Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

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TIMEOUT_INTEN : Receive FIFO Time-out Interrupt Enable
bits : 21 - 21 (1 bit)
access : read-write

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RX_THRESHOLD : Received FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0.
bits : 24 - 25 (2 bit)
access : read-write

TX_THRESHOLD : Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0.
bits : 28 - 29 (2 bit)
access : read-write

RX_INTSTS : Receive FIFO Threshold Interrupt Status (read only)
bits : 0 - 0 (1 bit)
access : read-only

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RX_OVERRUN : Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself.
bits : 2 - 2 (1 bit)
access : read-write

TX_INTSTS : Transmit FIFO Threshold Interrupt Status (read only)
bits : 4 - 4 (1 bit)
access : read-only

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SLV_START_INTSTS : Slave Start Interrupt Status\nIt is used to dedicate that the transfer has started in slave 3-wire mode. It's a mutual mirror bit of SPI_CNTRL2[11].
bits : 11 - 11 (1 bit)
access : read-write

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RX_FIFO_COUNT : Receive FIFO Data Count (read only)\nIndicates the valid data count of receive FIFO buffer.
bits : 12 - 15 (4 bit)
access : read-only

IF : SPI Unit Transfer Interrupt Flag\nIt's a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself.
bits : 16 - 16 (1 bit)
access : read-write

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TIMEOUT : Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
bits : 20 - 20 (1 bit)
access : read-write

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RX_EMPTY : Receive FIFO Buffer Empty Indicator (read only)\nIt's a mutual mirror bit of SPI_CNTRL[24].
bits : 24 - 24 (1 bit)
access : read-only

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RX_FULL : Receive FIFO Buffer Full Indicator (read only) \nIt's a mutual mirror bit of SPI_CNTRL[25].
bits : 25 - 25 (1 bit)
access : read-only

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TX_EMPTY : Transmit FIFO Buffer Empty Indicator (read only) \nIt's a mutual mirror bit of SPI_CNTRL[26].
bits : 26 - 26 (1 bit)
access : read-only

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TX_FULL : Transmit FIFO Buffer Full Indicator (read only)\nIt's a mutual mirror bit of SPI_CNTRL[27].
bits : 27 - 27 (1 bit)
access : read-only

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TX_FIFO_COUNT : Transmit FIFO Data Count (read only)\nIndicates the valid data count of transmit FIFO buffer.
bits : 28 - 31 (4 bit)
access : read-only

SSR : Slave Select Control Bits (Master only) If AUTOSS bit is cleared, writing 1 to this field sets the SPISSx line to active state and writing 0 sets the line back to inactive state. If AUTOSS bit is set, writing 0 to this field will keep the SPISSx line at inactive state writing 1 to this field will select the SPISSx line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPISSx is specified in SS_LVL.
bits : 0 - 0 (1 bit)
access : read-write

SS_LVL : Slave Select Active Level\nIt defines the active status of slave select signal (SPISSx).
bits : 2 - 2 (1 bit)
access : read-write

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AUTOSS : Automatic Slave Select Function Enable Bit (Master only)
bits : 3 - 3 (1 bit)
access : read-write

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SS_LTRIG : Slave Select Level Trigger Enable Bit (Slave only)
bits : 4 - 4 (1 bit)
access : read-write

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LTRIG_FLAG : Level Trigger Accomplish Flag\nIn slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done.\nNote: This bit is READ only
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.