\n
address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x44 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
ADC Data Register 0
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RSLT : A/D Conversion Result\nThis field contains conversion result of ADC.
bits : 0 - 15 (16 bit)
access : read-only
OVERRUN : Over Run Flag (Read Only)\nIf converted data in RSLT has not been read before new conversion result is loaded to this register, OVERRUN is set to 1. It is cleared by hardware after ADDR register is read.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Data in RSLT is recent conversion result
#1 : 1
Data in RSLT is overwrite
End of enumeration elements list.
VALID : Valid Flag \nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.\nThis is a read only bit
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
Data in RSLT bits is not valid
#1 : 1
Data in RSLT bits is valid
End of enumeration elements list.
ADC Data Register 4
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Data Register 5
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Data Register 6
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Data Register 7
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Control Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADEN : A/D Converter Enable\nBefore starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit power consumption.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
ADIE : A/D Interrupt Enable\nA/D conversion end interrupt request is generated if ADIE bit is set to 1.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable A/D interrupt function
#1 : 1
Enable A/D interrupt function
End of enumeration elements list.
ADMD : A/D Converter Operation Mode
When changing the operation mode, software should disable ADST bit firstly.
Note: In Burst Mode, the A/D result data always at Data Register 0.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Single conversion
#01 : 1
Burst conversion
#10 : 2
Single-cycle scan
#11 : 3
Continuous scan
End of enumeration elements list.
TRGS : Hardware Trigger Source\nSoftware should disable TRGEN and ADST before change TRGS. \nIn hardware trigger mode, the ADST bit is set by the external trigger from STADC.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
A/D conversion is started by external STADC pin
#11 : 3
A/D conversion is started by PWM trigger
End of enumeration elements list.
TRGCOND : External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state for edge trigger.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Low level
#01 : 1
High level
#10 : 2
Falling edge
#11 : 3
Rising edge
End of enumeration elements list.
TRGEN : External Trigger Enable\nEnable or disable triggering of A/D conversion by external STADC pin or PWM trigger.\nADC external trigger function is only supported in single-cycle scan mode.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
DIFFEN : Differential Input Mode Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
single-end analog input mode
#1 : 1
differential analog input mode
End of enumeration elements list.
ADST : A/D Conversion Start\nADST bit can be set to 1 from two sources: software and external pin STADC. ADST will be cleared to 0 by hardware automatically at the ends of single mode and single-cycle scan mode. In continuous scan and burst modes, A/D conversion is continuously performed until software write 0 to this bit or chip reset.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion stopped and A/D converter enter idle state
#1 : 1
Conversion start
End of enumeration elements list.
DMOF : A/D differential input Mode Output Format
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
A/D Conversion result will be filled in RSLT at ADDRx registers with unsigned format
#1 : 1
A/D Conversion result will be filled in RSLT at ADDRx registers with 2'complement format
End of enumeration elements list.
ADC Channel Enable Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN0 : Analog Input Channel 0 Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
CHEN1 : Analog Input Channel 1 Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
CHEN2 : Analog Input Channel 2 Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
CHEN3 : Analog Input Channel 3 Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
CHEN4 : Analog Input Channel 4 Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
CHEN5 : Analog Input Channel 5 Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
CHEN6 : Analog Input Channel 6 Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
CHEN7 : Analog Input Channel 7 Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
PRESEL : Analog Input Channel 7 select\nNote:\nWhen software select the band-gap voltage as the analog input source of ADC channel 7, ADC clock rate needs to be limited to lower than 300 KHz.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
External Analog Input
#01 : 1
Internal Bandgap voltage
#10 : 2
Internal temperature sensor
#11 : 3
Reserved
End of enumeration elements list.
ADC Compare Register 0
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPEN : Compare Enable\nSet this bit to 1 to enable ADC controller to compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADDR register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable compare function
#1 : 1
Enable compare function
End of enumeration elements list.
CMPIE : Compare Interrupt Enable\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPFx bit will be asserted, in the meanwhile, if CMPIE is set to 1, a compare interrupt request is generated.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable compare function interrupt
#1 : 1
Enable compare function interrupt
End of enumeration elements list.
CMPCOND : Compare Condition\nNote: When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one
#1 : 1
Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one
End of enumeration elements list.
CMPCH : Compare Channel Selection
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
#000 : 0
Channel 0 conversion result is selected to be compared
#001 : 1
Channel 1 conversion result is selected to be compared
#010 : 2
Channel 2 conversion result is selected to be compared
#011 : 3
Channel 3 conversion result is selected to be compared
#100 : 4
Channel 4 conversion result is selected to be compared
#101 : 5
Channel 5 conversion result is selected to be compared
#110 : 6
Channel 6 conversion result is selected to be compared
#111 : 7
Channel 7 conversion result is selected to be compared
End of enumeration elements list.
CMPMATCNT : Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set.
bits : 8 - 11 (4 bit)
access : read-write
CMPD : Comparison Data\nThe 12 bits data is used to compare with conversion result of specified channel. \nWhen DMOF bit is set to 0, ADC comparator compares CMPD with conversion result with unsigned format. CMPD should be filled in unsigned format.\nWhen DMOF bit is set to 1, ADC comparator compares CMPD with conversion result with 2'complement format. CMPD should be filled in 2'complement format.
bits : 16 - 27 (12 bit)
access : read-write
ADC Compare Register 1
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Status Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADF : A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion.\nADF is set to 1 at these three conditions:\nWhen A/D conversion ends in single mode\nWhen A/D conversion ends on all specified channels in scan mode.\nWhen more than 4 samples in FIFO in Burst mode.\nThis flag can be cleared by writing 1 to self.
bits : 0 - 0 (1 bit)
access : read-write
CMPF0 : Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1. And it is cleared by writing 1 to self.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion result in ADDR does not meet ADCMPR0 setting
#1 : 1
Conversion result in ADDR meets ADCMPR0setting
End of enumeration elements list.
CMPF1 : Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1. And it is cleared by writing 1 to self.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion result in ADDR does not meet ADCMPR1 setting
#1 : 1
Conversion result in ADDR meets ADCMPR1 setting
End of enumeration elements list.
BUSY : BUSY/IDLE\nThis bit is mirror of as ADST bit in ADCR.\nIt is read only.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
A/D converter is in idle state
#1 : 1
A/D converter is busy at conversion
End of enumeration elements list.
CHANNEL : Current Conversion Channel\nIt is read only.
bits : 4 - 6 (3 bit)
access : read-write
VALID : Data Valid flag (Read Only)\nIt is a mirror of VALID bit in ADDRx\nWhen ADC in Burst Mode, and the FIFO is valid, VALID[7:0] will all set to 1.
bits : 8 - 15 (8 bit)
access : read-only
OVERRUN : Over Run flag (Read Only)\nIt is a mirror to OVERRUN bit in ADDRx\nWhen ADC in Burst Mode, and the FIFO is overrun, OVERRUN[7:0] will all set to 1.
bits : 16 - 23 (8 bit)
access : read-only
ADC Data Register 1
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Trigger Delay Control Register
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PTDT : PWM Trigger Delay Time\nSet this field will delay ADC start conversion time after PWM trigger is coming.\nPWM trigger delay time is (4 * PTDT) * system clock
bits : 0 - 7 (8 bit)
access : read-write
ADC Data Register 2
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Data Register 3
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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