\n

DIV

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected

Registers

DIVIDEND

DIVSTS

DIVISOR

DIVQUO

DIVREM


DIVIDEND

Dividend Source Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIVIDEND DIVIDEND read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Dividend

Dividend : Dividend Source.\nThis register is given the dividend of divider before calculation starts.
bits : 0 - 31 (32 bit)
access : read-write


DIVSTS

Divider Status Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIVSTS DIVSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV_FINISH DIV0

DIV_FINISH : Divider operation finished.\nThis register is read only.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

The divider calculation is not yet

#1 : 1

The divider calculation is finished

End of enumeration elements list.

DIV0 : Divisor zero warning.\n1: The divisor is 0.\n0: The divisor is not 0.\nThis register is read only.
bits : 1 - 1 (1 bit)
access : read-write


DIVISOR

Divisor Source Resister
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIVISOR DIVISOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Divisor

Divisor : Divisor Source.\nThis register is given the divisor of divider before calculation starts.\nNote: when this register is written, hardware divider will start calculate
bits : 0 - 15 (16 bit)
access : read-write


DIVQUO

Quotient Result Resister
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIVQUO DIVQUO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Quotient

Quotient : Quotient Result\nThis register holds the quotient result of divider after calculation complete.
bits : 0 - 31 (32 bit)
access : read-write


DIVREM

Reminder Result Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIVREM DIVREM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reminder

Reminder : Reminder Result\nThis register holds the reminder result of divider after calculation complete.
bits : 0 - 15 (16 bit)
access : read-write



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