\n

GCR

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x100 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x50 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x24 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x30 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x18 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PDID

CPR

REGWRPROT

BODCR

TEMPCR

PORCR

GPA_MFP

GPB_MFP

GPC_MFP

GPD_MFP

RSTSRC

GPE_MFP

ALT_MFP

IPRSTC1

IPRSTC2


PDID

Part Device Identification Number Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PDID PDID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDID

PDID : Part Device Identification Number\nThis register reflects device part number code. S/W can read this register to identify which device is used.
bits : 0 - 31 (32 bit)
access : read-only


CPR

Chip Performance Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPR CPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HPE

HPE : High Performance Enable (Write-Protection Bit)\nThis bit is used to control chip operation performance.\nWhen this bit set, internal RAM and GPIO access is working with zero wait state, and Flash controller will predict next address more efficiently. The high performance is enabled without limiting by chip operation frequency.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Chip operation at normal mode

#1 : 1

Chip operation at high performance mode

End of enumeration elements list.


REGWRPROT

Register Write Protect Register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGWRPROT REGWRPROT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGWRPROT

REGWRPROT : Register Write-Protection Code (Write Only) Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 59h , 16h , 88h to this field. After this sequence is completed, the REGPROTDIS bit will be set to 1 and write-protection registers can be normal write. Register Write-Protection Disable index (Read only) The Protected registers are: IPRSTC1: address 0x5000_0008 CPR: address 0x5000_0010 (Low Density only) BODCR: address 0x5000_0018 PORCR: address 0x5000_0024 PWRCON: address 0x5000_0200 (bit[6] is not protected for power wake-up interrupt clear) APBCLK bit[0]: address 0x5000_0208 (bit[0] is watchdog clock enable) CLKSEL0: address 0x5000_0210 (for HCLK and CPU STCLK clock source select) CLKSEL1 bit[1:0]: address 0x5000_0214 (for watchdog clock source select) ISPCON: address 0x5000_C000 (Flash ISP Control register) ISPTRG: address 0x5000_C010 (ISP Trigger Control register) WTCR: address 0x4000_4000 FATCON: address 0x5000_C018
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

0 : 0

Write-protection Enabled for writing protected registers. Any write to the protected register is ignored

1 : 1

Write-protection Disabled for writing protected registers

End of enumeration elements list.


BODCR

Brown-out Detector Control Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BODCR BODCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BOD_EN BOD_VL BOD_RSTEN BOD_INTF BOD_LPM BOD_OUT LVR_EN

BOD_EN : Brown-out Detector Enable (write-protection bit) The default value is set by flash controller user configuration register config0 bit[23] This bit is the protected bit, which means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Brown-out Detector function Disabled

#1 : 1

Brown-out Detector function Enabled

End of enumeration elements list.

BOD_VL : Brown-out Detector Threshold Voltage Selection (Write-Protection Bit)\n
bits : 1 - 2 (2 bit)
access : read-write

BOD_RSTEN : Brown-out Reset Enable (Write-Protection Bit) While the BOD function is enabled (BOD_EN high) and BOD interrupt function is enabled (BOD_RSTEN low), BOD will assert an interrupt if BOD_OUT is high. BOD interrupt will keep till to the BOD_EN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BOD_EN low). The default value is set by flash controller user configuration register config0 bit[20]. This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Brown-out INTERRUPT function Enabled

#1 : 1

Brown-out RESET function Enabled

End of enumeration elements list.

BOD_INTF : Brown-out Detector Interrupt Flag\nWrite 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BOD_VL setting

#1 : 1

When Brown-out Detector detects the VDD is dropped down through the voltage of BOD_VL setting or the VDD is raised up through the voltage of BOD_VL setting, this bit is set to 1 and the Brown-out interrupt is requested if Brown-out interrupt is enabled

End of enumeration elements list.

BOD_LPM : Brown-out Detector Low power Mode (Write-Protection Bit) The BOD consumes about 100 uA in Normal mode, and the low power mode can reduce the current to about 1/10 but slow the BOD response. This bit is the protected bit, which means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

BOD operated in Normal mode (default)

#1 : 1

BOD low power mode Enabled

End of enumeration elements list.

BOD_OUT : Brown-out Detector output status\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Brown-out Detector output status is 0. It means the detected voltage is higher than BOD_VL setting or BOD_EN is 0

#1 : 1

Brown-out Detector output status is 1. It means the detected voltage is lower than BOD_VL setting. If the BOD_EN is 0, BOD function disabled , this bit always responds 0

End of enumeration elements list.

LVR_EN : Low Voltage Reset Enable (Write-Protection Bit) The LVR function reset the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled in default. This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Low Voltage Reset function Disabled

#1 : 1

Low Voltage Reset function Enabled - After enabling the bit, the LVR function will be active with 100uS delay for LVR output stable. (Default)

End of enumeration elements list.


TEMPCR

Temperature Sensor Control Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TEMPCR TEMPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VTEMP_EN

VTEMP_EN : Temperature Sensor Enable\nThis bit is used to enable/disable temperature sensor function.\nAfter this bit is set to 1, the value of temperature can be obtained from ADC conversion result by ADC channel selecting channel 7 and alternative multiplexer channel selecting temperature sensor. Please refer to the ADC function chapter for detailed ADC conversion function description.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Temperature sensor function Disabled (default)

#1 : 1

Temperature sensor function Enabled

End of enumeration elements list.


PORCR

Power-On-reset Controller Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PORCR PORCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POR_DIS_CODE

POR_DIS_CODE : Power-On-Reset Enable Control (Write-protection Bits) When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: /RESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function This bit is the protected bit, which means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 15 (16 bit)
access : read-write


GPA_MFP

GPIOA Multiple Function and Input Type Control Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPA_MFP GPA_MFP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPA_MFP0 GPA_MFP1 GPA_MFP2 GPA_MFP3 GPA_MFP4 GPA_MFP5 GPA_MFP6 GPA_MFP7 GPA_MFP8 GPA_MFP9 GPA_MFP10 GPA_MFP11 GPA_MFP12 GPA_MFP13 GPA_MFP14 GPA_MFP15 GPA_TYPEn

GPA_MFP0 : PA.0 Pin Function Selection\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOA[0] selected to the pin PA.0

#1 : 1

ADC0 (Analog-to-Digital converter channel 0) function selected to the pin PA.0

End of enumeration elements list.

GPA_MFP1 : PA.1 Pin Function Selection\n
bits : 1 - 1 (1 bit)
access : read-write

GPA_MFP2 : PA.2 Pin Function Selection\n
bits : 2 - 2 (1 bit)
access : read-write

GPA_MFP3 : PA.3 Pin Function Selection\n
bits : 3 - 3 (1 bit)
access : read-write

GPA_MFP4 : PA.4 Pin Function Selection\n
bits : 4 - 4 (1 bit)
access : read-write

GPA_MFP5 : PA.5 Pin Function Selection\n
bits : 5 - 5 (1 bit)
access : read-write

GPA_MFP6 : PA.6 Pin Function Selection\n
bits : 6 - 6 (1 bit)
access : read-write

GPA_MFP7 : PA.7 Pin Function Selection\n
bits : 7 - 7 (1 bit)
access : read-write

GPA_MFP8 : PA.8 Pin Function Selection\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOA[8] selected to the pin PA.8

#1 : 1

I2C0 SDA function selected to the pin PA.8

End of enumeration elements list.

GPA_MFP9 : PA.9 Pin Function Selection\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOA[9] selected to the pin PA.9

#1 : 1

I2C0 SCL function selected to the pin PA.9

End of enumeration elements list.

GPA_MFP10 : PA.10 Pin Function Selection\n
bits : 10 - 10 (1 bit)
access : read-write

GPA_MFP11 : PA.11 Pin Function Selection\n
bits : 11 - 11 (1 bit)
access : read-write

GPA_MFP12 : PA.12 Pin Function Selection\n
bits : 12 - 12 (1 bit)
access : read-write

GPA_MFP13 : PA.13 Pin Function Selection\n
bits : 13 - 13 (1 bit)
access : read-write

GPA_MFP14 : PA.14 Pin Function Selection\n
bits : 14 - 14 (1 bit)
access : read-write

GPA_MFP15 : PA.15 Pin Function Selection\n
bits : 15 - 15 (1 bit)
access : read-write

GPA_TYPEn : None
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

0 : 0

GPIOA[15:0] I/O input Schmitt Trigger function Disabled

1 : 1

GPIOA[15:0] I/O input Schmitt Trigger function Enabled

End of enumeration elements list.


GPB_MFP

GPIOB Multiple Function and Input Type Control Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPB_MFP GPB_MFP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPB_MFP0 GPB_MFP1 GPB_MFP2 GPB_MFP3 GPB_MFP4 GPB_MFP5 GPB_MFP6 GPB_MFP7 GPB_MFP8 GPB_MFP9 GPB_MFP10 GPB_MFP11 GPB_MFP12 GPB_MFP13 GPB_MFP14 GPB_MFP15 GPB_TYPEn

GPB_MFP0 : PB.0 Pin Function Selection\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOB[0] selected to the pin PB.0

#1 : 1

UART0 RXD function selected to the pin PB.0

End of enumeration elements list.

GPB_MFP1 : PB.1 Pin Function Selection\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOB[1] selected to the pin PB.1

#1 : 1

UART0 TXD function selected to the pin PB.1

End of enumeration elements list.

GPB_MFP2 : PB.2 Pin Function Selection\n
bits : 2 - 2 (1 bit)
access : read-write

GPB_MFP3 : PB.3 Pin Function Selection\n
bits : 3 - 3 (1 bit)
access : read-write

GPB_MFP4 : PB.4 Pin Function Selection\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOB[4] selected to the pin PB.4

#1 : 1

UART1 RXD function selected to the pin PB.4

End of enumeration elements list.

GPB_MFP5 : PB. 5 Pin Function Selection\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOB[5] is selected to the pin PB.5

#1 : 1

UART1 TXD function is selected to the pin PB.5

End of enumeration elements list.

GPB_MFP6 : PB.6 Pin Function Selection\n
bits : 6 - 6 (1 bit)
access : read-write

GPB_MFP7 : PB.7 Pin Function Selection\n
bits : 7 - 7 (1 bit)
access : read-write

GPB_MFP8 : PB.8 Pin Function Selection\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOB[8] selected to the pin PB.8

#1 : 1

TM0 (Timer/Counter external trigger clock input) function selected to the pin PB.8

End of enumeration elements list.

GPB_MFP9 : PB.9 Pin Function Selection\n
bits : 9 - 9 (1 bit)
access : read-write

GPB_MFP10 : PB.10 Pin Function Selection\n
bits : 10 - 10 (1 bit)
access : read-write

GPB_MFP11 : PB.11 Pin Function Selection\n
bits : 11 - 11 (1 bit)
access : read-write

GPB_MFP12 : PB.12 Pin Function Selection\n
bits : 12 - 12 (1 bit)
access : read-write

GPB_MFP13 : PB.13 Pin Function Selection\n
bits : 13 - 13 (1 bit)
access : read-write

GPB_MFP14 : PB.14 Pin Function Selection\n
bits : 14 - 14 (1 bit)
access : read-write

GPB_MFP15 : PB.15 Pin Function Selection\n
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOB[15] selected to the pin PB.15

#1 : 1

External Interrupt INT1 function selected to the pin PB.15

End of enumeration elements list.

GPB_TYPEn : None
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

0 : 0

GPIOB[15:0] I/O input Schmitt Trigger function Disabled

1 : 1

GPIOB[15:0] I/O input Schmitt Trigger function Enabled

End of enumeration elements list.


GPC_MFP

GPIOC Multiple Function and Input Type Control Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPC_MFP GPC_MFP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPC_MFP0 GPC_MFP1 GPC_MFP2 GPC_MFP3 GPC_MFP4 GPC_MFP5 GPC_MFP6 GPC_MFP7 GPC_MFP8 GPC_MFP9 GPC_MFP10 GPC_MFP11 GPC_MFP12 GPC_MFP13 GPC_MFP14 GPC_MFP15 GPC_TYPEn

GPC_MFP0 : PC.0 Pin Function Selection\n
bits : 0 - 0 (1 bit)
access : read-write

GPC_MFP1 : PC.1 Pin Function Selection\n
bits : 1 - 1 (1 bit)
access : read-write

GPC_MFP2 : PC.2 Pin Function Selection\n
bits : 2 - 2 (1 bit)
access : read-write

GPC_MFP3 : PC.3 Pin Function Selection\n
bits : 3 - 3 (1 bit)
access : read-write

GPC_MFP4 : PC.4 Pin Function Selection\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOC[4] is selected to the pin PC.4

#1 : 1

SPI0 MISO1 (master input, slave output pin-1) function is selected to the pin PC.4

End of enumeration elements list.

GPC_MFP5 : PC.5 Pin Function Selection\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOC[5] is selected to the pin PC.5

#1 : 1

SPI0 MOSI1 (master output, slave input pin-1) function is selected to the pin PC.5

End of enumeration elements list.

GPC_MFP6 : PC.6 Pin Function Selection\n
bits : 6 - 6 (1 bit)
access : read-write

GPC_MFP7 : PC.7 Pin Function Selection\n
bits : 7 - 7 (1 bit)
access : read-write

GPC_MFP8 : PC.8 Pin Function Selection\n
bits : 8 - 8 (1 bit)
access : read-write

GPC_MFP9 : PC.9 Pin Function Selection\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOC[9] selected to the pin PC.9

#1 : 1

SPI1 SPICLK function selected to the pin PC.9

End of enumeration elements list.

GPC_MFP10 : PC.10 Pin Function Selection\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOC[10] is selected to the pin PC.10

#1 : 1

SPI1 MISO0 (master input, slave output pin-0) function selected to the pin PC.10

End of enumeration elements list.

GPC_MFP11 : PC.11 Pin Function Selection\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOC[11] selected to the pin PC.11

#1 : 1

SPI1 MOSI0 (master output, slave input pin-0) function selected to the pin PC.11

End of enumeration elements list.

GPC_MFP12 : PC.12 Pin Function Selection\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOC[12] selected to the pin PC.12

#1 : 1

SPI1 MISO1 (master input, slave output pin-1) function selected to the pin PC.12

End of enumeration elements list.

GPC_MFP13 : PC.13 Pin Function Selection\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOC[13] selected to the pin PC.13

#1 : 1

SPI1 MOSI1 (master output, slave input pin-1) function selected to the pin PC.13

End of enumeration elements list.

GPC_MFP14 : PC.14 Pin Function Selection\n
bits : 14 - 14 (1 bit)
access : read-write

GPC_MFP15 : PC.15 Pin Function Selection\n
bits : 15 - 15 (1 bit)
access : read-write

GPC_TYPEn : None
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

0 : 0

GPIOC[15:0] I/O input Schmitt Trigger function Disabled

1 : 1

GPIOC[15:0] I/O input Schmitt Trigger function Enabled

End of enumeration elements list.


GPD_MFP

GPIOD Multiple Function and Input Type Control Register
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPD_MFP GPD_MFP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPD_MFP0 GPD_MFP1 GPD_MFP2 GPD_MFP3 GPD_MFP4 GPD_MFP5 GPD_MFP6 GPD_MFP7 GPD_MFP8 GPD_MFP9 GPD_MFP10 GPD_MFP11 GPD_MFP12 GPD_MFP13 GPD_MFP14 GPD_MFP15 GPD_TYPEn

GPD_MFP0 : PD.0 Pin Function Selection (NuMicro( NUC100/NUC120 Medium Density Only)\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOD[0] selected to the pin PD.0

#1 : 1

SPI2 SS20 function selected to the pin PD.0

End of enumeration elements list.

GPD_MFP1 : PD.1 Pin Function Selection\nFor NuMicro( NUC100/NUC120 Medium Density:\nFor NuMicro( NUC100/NUC120 Low Density:\nReserved
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOD[1] selected to the pin PD.1

#1 : 1

SPI2 SPICLK function selected to the pin PD.1

End of enumeration elements list.

GPD_MFP2 : PD.2 Pin Function Selection\nFor NuMicro( NUC100/NUC120 Medium Density:\nFor NuMicro( NUC100/NUC120 Low Density:\nReserved
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOD[2] selected to the pin PD.2

#1 : 1

SPI2 MISO0 (master input, slave output pin-0) function selected to the pin PD.2

End of enumeration elements list.

GPD_MFP3 : PD.3 Pin Function Selection\nFor NuMicro( NUC100/NUC120 Medium Density:\nFor NuMicro( NUC100/NUC120 Low Density:\nReserved
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOD[3] selected to the pin PD.3

#1 : 1

SPI2 MOSI0 (master output, slave input pin-0) function selected to the pin PD.3

End of enumeration elements list.

GPD_MFP4 : PD.4 Pin Function Selection (NuMicro( NUC100/NUC120 Medium Density Only)\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOD[4]is selected to the pin PD.4

#1 : 1

SPI2 MISO1 (master input, slave output pin-1) function selected to the pin PD.4

End of enumeration elements list.

GPD_MFP5 : PD.5 Pin Function Selection (NuMicro( NUC100/NUC120 Medium Density Only)\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOD[5] is selected to the pin PD.5

#1 : 1

SPI2 MOSI1 (master output, slave input pin-1) function selected to the pin PD.5

End of enumeration elements list.

GPD_MFP6 : Reserved
bits : 6 - 6 (1 bit)
access : read-write

GPD_MFP7 : Reserved
bits : 7 - 7 (1 bit)
access : read-write

GPD_MFP8 : PD.8 Pin Function Selection (NuMicro( NUC100/NUC120 Medium Density Only)\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOD[8] selected to the pin PD8

#1 : 1

SPI3 SS30 function selected to the pin PD8

End of enumeration elements list.

GPD_MFP9 : PD.9 Pin Function Selection (NuMicro( NUC100/NUC120 Medium Density Only)\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOD[9] selected to the pin PD.9

#1 : 1

SPI3 SPICLK function selected to the pin PD.9

End of enumeration elements list.

GPD_MFP10 : PD.10 Pin Function Selection (NuMicro( NUC100/NUC120 Medium Density Only)\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOD[10] selected to the pin PD.10

#1 : 1

SPI3 MISO0 (master input, slave output pin-0) function selected to the pin PD.10

End of enumeration elements list.

GPD_MFP11 : PD.11 Pin Function Selection (NuMicro( NUC100/NUC120 Medium Density Only)\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOD[11] selected to the pin PD.11

#1 : 1

SPI3 MOSI0 (master output, slave input pin-0) function selected to the pin PD.11

End of enumeration elements list.

GPD_MFP12 : PD.12 Pin Function Selection (NuMicro( NUC100/NUC120 Medium Density Only)\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOD[12] selected to the pin PD.12

#1 : 1

SPI3 MISO1 (master input, slave output pin-1) function selected to the pin PD.12

End of enumeration elements list.

GPD_MFP13 : PD.13 Pin Function Selection (NuMicro( NUC100/NUC120 Medium Density Only)\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOD[13] selected to the pin PD.13

#1 : 1

SPI3 MOSI1 (master output, slave input pin-1) function selected to the pin PD.13

End of enumeration elements list.

GPD_MFP14 : PD.14 Pin Function Selection (NuMicro( NUC100/NUC120 Medium Density Only)\n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOD[14] selected to the pin PD.14

#1 : 1

UART2 RXD function is selected to the pin PD.14

End of enumeration elements list.

GPD_MFP15 : PD.15 Pin Function Selection (NuMicro( NUC100/NUC120 Medium Density Only)\n
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOD[15] selected to the pin PD.15

#1 : 1

UART2 TXD function selected to the pin PD.15

End of enumeration elements list.

GPD_TYPEn : None
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

0 : 0

GPIOD[15:0] I/O input Schmitt Trigger function Disabled

1 : 1

GPIOD[15:0] I/O input Schmitt Trigger function Enabled

End of enumeration elements list.


RSTSRC

System Reset Source Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSTSRC RSTSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSTS_POR RSTS_RESET RSTS_WDT RSTS_LVR RSTS_BOD RSTS_SYS RSTS_CPU

RSTS_POR : The RSTS_POR flag is set by the reset signal from the Power-On Reset (POR) controller or bit CHIP_RST (IPRSTC1[0]) to indicate the previous reset source. Write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No reset from POR or CHIP_RST

#1 : 1

Power-On Reset (POR) or CHIP_RST had issued the reset signal to reset the system

End of enumeration elements list.

RSTS_RESET : The RSTS_RESET flag is set by the reset signal from the /RESET pin to indicate the previous reset source. Write 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No reset from /RESET pin

#1 : 1

Pin /RESET had issued the reset signal to reset the system

End of enumeration elements list.

RSTS_WDT : The RSTS_WDT flag is set by the reset signal from the watchdog timer to indicate the previous reset source. Write 1 to clear this bit to 0.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

No reset from watchdog timer

#1 : 1

Watchdog timer had issued the reset signal to reset the system

End of enumeration elements list.

RSTS_LVR : The RSTS_LVR flag is set by the reset signal from the Low-Voltage-Reset controller to indicate the previous reset source. Write 1 to clear this bit to 0.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

No reset from LVR

#1 : 1

LVR controller had issued the reset signal to reset the system

End of enumeration elements list.

RSTS_BOD : The RSTS_BOD flag is set by the reset signal from the Brown-out-Detector to indicate the previous reset source. Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

No reset from BOD

#1 : 1

BOD had issued the reset signal to reset the system

End of enumeration elements list.

RSTS_SYS : The RSTS_SYS flag is set by the reset signal from the Cortex_M0 kernel to indicate the previous reset source. Write 1 to clear this bit to 0.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

No reset from Cortex_M0

#1 : 1

Cortex_M0 had issued the reset signal to reset the system by writing 1 to bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex_M0 kernel

End of enumeration elements list.

RSTS_CPU : The RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) 1 to reset Cortex-M0 CPU kernel and Flash memory controller (FMC).\nWrite 1 to clear this bit to 0.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

No reset from CPU

#1 : 1

Cortex-M0 CPU kernel and FMC are reset by software setting CPU_RST to 1

End of enumeration elements list.


GPE_MFP

GPIOE Multiple Function and Input Type Control Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPE_MFP GPE_MFP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPE_MFP0 GPE_MFP1 GPE_MFP5 GPE_TYPEn

GPE_MFP0 : PE.0 Pin Function Selection (NuMicro( NUC100/NUC120 Medium Density Only)\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOE[0] selected to the pin PE.0

#1 : 1

PWM6 function selected to the pin PE.0

End of enumeration elements list.

GPE_MFP1 : PE.1 Pin Function Selection (NuMicro( NUC100/NUC120 Medium Density Only)\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOE[1] selected to the pin PE.1

#1 : 1

PWM7 function selected to the pin PE.1

End of enumeration elements list.

GPE_MFP5 : PE.5 Pin Function Selection (NuMicro( NUC100/NUC120 Medium Density Only)\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOE[5] selected to the pin PE.5

#1 : 1

PWM5 function selected to the pin PE.5

End of enumeration elements list.

GPE_TYPEn : Note: In this field, NuMicro( NUC100/NUC120 Low Density only has GPE_TYPE5 bit.
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

0 : 0

GPIOE[15:0] I/O input Schmitt Trigger function Disabled

1 : 1

GPIOE[15:0] I/O input Schmitt Trigger function Enabled

End of enumeration elements list.


ALT_MFP

Alternative Multiple Function Pin Control Register
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALT_MFP ALT_MFP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PB10_S01 PB9_S11 PA7_S21 PB14_S31 PB11_PWM4 PC0_I2SLRCLK PC1_I2SBCLK PC2_I2SDI PC3_I2SDO PA15_I2SMCLK PB12_CLKO EBI_EN EBI_MCLK_EN EBI_nWRL_EN EBI_nWRH_EN EBI_HB_EN0 EBI_HB_EN1 EBI_HB_EN2 EBI_HB_EN3 EBI_HB_EN4 EBI_HB_EN5 EBI_HB_EN6 EBI_HB_EN7

PB10_S01 : Bits PB10_S01 and GPB_MFP[10] determine the PB.10 function.\n
bits : 0 - 0 (1 bit)
access : read-write

PB9_S11 : Bits PB9_S11 and GPB_MFP[9] determine the PB.9 function.\n
bits : 1 - 1 (1 bit)
access : read-write

PA7_S21 : Bits PA7_S21, GPA_MFP[7] and EBI_EN (ALT_MFP[11]).determine the PA.7 function.\n
bits : 2 - 2 (1 bit)
access : read-write

PB14_S31 : Bits PB14_S31 and GPB_MFP[14] determine the PB.14 function.\n
bits : 3 - 3 (1 bit)
access : read-write

PB11_PWM4 : Bits PB11_PWM4 and GPB_MFP[11] determine the PB.11 function.\n
bits : 4 - 4 (1 bit)
access : read-write

PC0_I2SLRCLK : Bits PC0_I2SLRCLK and GPC_MFP[0] determine the PC.0 function.\n
bits : 5 - 5 (1 bit)
access : read-write

PC1_I2SBCLK : Bits PC1_I2SBCLK and GPC_MFP[1] determine the PC.1 function.\n
bits : 6 - 6 (1 bit)
access : read-write

PC2_I2SDI : Bits PC2_I2SDI and GPC_MFP[2] determine the PC.2 function.\n
bits : 7 - 7 (1 bit)
access : read-write

PC3_I2SDO : Bits PC3_I2SDO and GPC_MFP[3] determine the PC.3 function.\n
bits : 8 - 8 (1 bit)
access : read-write

PA15_I2SMCLK : Bits PA15_I2SMCLK and GPA_MFP[15] determine the PA.15 function.\n
bits : 9 - 9 (1 bit)
access : read-write

PB12_CLKO : Bits PB12_CLKO, GPB_MFP[12] and EBI_EN (ALT_MFP[11]) determine the PB.12 function.\n
bits : 10 - 10 (1 bit)
access : read-write

EBI_EN : EBI_EN is used to switch GPIO function to EBI function (AD[15:0], ALE, RE, WE, CS, MCLK), which needs additional registers EBI_EN[7:0] and EBI_MCLK_EN for some GPIO to switch to EBI function(AD[15:8], MCLK).\n
bits : 11 - 11 (1 bit)
access : read-write

EBI_MCLK_EN : Bits EBI_MCLK_EN, EBI_EN and GPC_MFP[8] determine the PC.8 function.\n
bits : 12 - 12 (1 bit)
access : read-write

EBI_nWRL_EN : Bits EBI_nWRL_EN, EBI_EN and GPB_MFP[2] determine the PB.2 function.\n
bits : 13 - 13 (1 bit)
access : read-write

EBI_nWRH_EN : Bits EBI_nWRH_EN, EBI_EN and GPB_MFP[3] determine the PB.3 function.\n
bits : 14 - 14 (1 bit)
access : read-write

EBI_HB_EN0 : Bits EBI_HB_EN[0], EBI_EN and GPA_MFP[5] determine the PA.5 function.\n
bits : 16 - 16 (1 bit)
access : read-write

EBI_HB_EN1 : Bits EBI_HB_EN[1], EBI_EN and GPA_MFP[4] determine the PA.4 function.\n
bits : 17 - 17 (1 bit)
access : read-write

EBI_HB_EN2 : Bits EBI_HB_EN[2], EBI_EN and GPA_MFP[3] determine the PA.3 function.\n
bits : 18 - 18 (1 bit)
access : read-write

EBI_HB_EN3 : Bits EBI_HB_EN[3], EBI_EN and GPA_MFP[2] determine the PA.2 function.\n
bits : 19 - 19 (1 bit)
access : read-write

EBI_HB_EN4 : Bits EBI_HB_EN[4], EBI_EN and GPA_MFP[1] determine the PA.1 function.\n
bits : 20 - 20 (1 bit)
access : read-write

EBI_HB_EN5 : Bits EBI_HB_EN[5], EBI_EN and GPA_MFP[12] determine the PA.12 function.\n
bits : 21 - 21 (1 bit)
access : read-write

EBI_HB_EN6 : Bits EBI_HB_EN[6], EBI_EN and GPA_MFP[13] determine the PA.13 function.\n
bits : 22 - 22 (1 bit)
access : read-write

EBI_HB_EN7 : EBI_HB_EN is used to switch GPIO function to EBI address/data bus high byte (AD[15:8]), EBI_HB_EN, EBI_EN and the corresponding GPx_MFP[y] determine the Px.y function.
bits : 23 - 23 (1 bit)
access : read-write


IPRSTC1

IP Reset Control Register 1
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRSTC1 IPRSTC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIP_RST CPU_RST PDMA_RST EBI_RST

CHIP_RST : CHIP One-shot Reset (Write-Protection Bit) Setting this bit will reset the whole chip, including CPU kernel and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. The CHIP_RST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload. About the difference between CHIP_RST and SYSRESETREQ, please refer to section 5.2.2 This bit is the protected bit. It means programming this bit needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

CHIP normal operation

#1 : 1

CHIP one-shot reset

End of enumeration elements list.

CPU_RST : CPU Kernel one-shot reset (Write-protection Bit) Setting this bit will only reset the CPU kernel and Flash Memory Controller(FMC), and this bit will automatically return 0 after two clock cycles This bit is the protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

CPU normal operation

#1 : 1

CPU one-shot reset

End of enumeration elements list.

PDMA_RST : PDMA Controller Reset (Write-protection Bit in NuMicro( NUC100/NUC120 Low Density) Setting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0 to release from reset state. This bit is the protected bit, which means programming this bit needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

PDMA controller normal operation

#1 : 1

PDMA controller reset

End of enumeration elements list.

EBI_RST : EBI Controller Reset (NuMicro( NUC100/NUC120 Low Density 64 pin Package Only) (Write-protection Bit in NuMicro( NUC100/NUC120 Low Density 64-pin Package) Set this bit to 1 will generate a reset signal to the EBI. User needs to set this bit to 0 to release from the reset state. This bit is the protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

EBI controller normal operation

#1 : 1

EBI controller reset

End of enumeration elements list.


IPRSTC2

IP Reset Control Register 2
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRSTC2 IPRSTC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_RST TMR0_RST TMR1_RST TMR2_RST TMR3_RST I2C0_RST I2C1_RST SPI0_RST SPI1_RST SPI2_RST SPI3_RST UART0_RST UART1_RST UART2_RST PWM03_RST PWM47_RST ACMP_RST PS2_RST USBD_RST ADC_RST I2S_RST

GPIO_RST : GPIO controller Reset\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO controller normal operation

#1 : 1

GPIO controller reset

End of enumeration elements list.

TMR0_RST : Timer0 controller Reset\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer0 controller normal operation

#1 : 1

Timer0 controller reset

End of enumeration elements list.

TMR1_RST : Timer1 controller Reset\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer1 controller normal operation

#1 : 1

Timer1 controller reset

End of enumeration elements list.

TMR2_RST : Timer2 controller Reset\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer2 controller normal operation

#1 : 1

Timer2 controller reset

End of enumeration elements list.

TMR3_RST : Timer3 controller Reset\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer3 controller normal operation

#1 : 1

Timer3 controller reset

End of enumeration elements list.

I2C0_RST : I2C0 controller Reset\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C0 controller normal operation

#1 : 1

I2C0 controller reset

End of enumeration elements list.

I2C1_RST : I2C1 controller Reset\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C1 controller normal operation

#1 : 1

I2C1 controller reset

End of enumeration elements list.

SPI0_RST : SPI0 controller Reset\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI0 controller normal operation

#1 : 1

SPI0 controller reset

End of enumeration elements list.

SPI1_RST : SPI1 controller Reset\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI1 controller normal operation

#1 : 1

SPI1 controller reset

End of enumeration elements list.

SPI2_RST : SPI2 controller Reset (NuMicro( NUC100/NUC120 Medium Density Only)\n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI2 controller normal operation

#1 : 1

SPI2 controller reset

End of enumeration elements list.

SPI3_RST : SPI3 controller Reset (NuMicro( NUC100/NUC120 Medium Density Only)\n
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI3 controller normal operation

#1 : 1

SPI3 controller reset

End of enumeration elements list.

UART0_RST : UART0 controller Reset\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART0 controller normal operation

#1 : 1

UART0 controller reset

End of enumeration elements list.

UART1_RST : UART1 controller Reset\n
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART1 controller normal operation

#1 : 1

UART1 controller reset

End of enumeration elements list.

UART2_RST : UART2 controller Reset (NuMicro( NUC100/NUC120 Medium Density Only)\n
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART2 controller normal operation

#1 : 1

UART2 controller reset

End of enumeration elements list.

PWM03_RST : PWM03 controller Reset\n
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM03 controller normal operation

#1 : 1

PWM03 controller reset

End of enumeration elements list.

PWM47_RST : PWM47 controller Reset (NuMicro( NUC100/NUC120 Medium Density Only)\n
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM47 controller normal operation

#1 : 1

PWM47 controller reset

End of enumeration elements list.

ACMP_RST : Analog Comparator Controller Reset\n
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

Analog Comparator controller normal operation

#1 : 1

Analog Comparator controller reset

End of enumeration elements list.

PS2_RST : PS/2 Controller Reset\n
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

PS/2 controller normal operation

#1 : 1

PS/2 controller reset

End of enumeration elements list.

USBD_RST : USB Device Controller Reset\n
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

USB device controller normal operation

#1 : 1

USB device controller reset

End of enumeration elements list.

ADC_RST : ADC Controller Reset\n
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

ADC controller normal operation

#1 : 1

ADC controller reset

End of enumeration elements list.

I2S_RST : I2S Controller Reset\n
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2S controller normal operation

#1 : 1

I2S controller reset

End of enumeration elements list.



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