\n

RTC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected

Registers

INIR

CLR

TSSR

DWR

TAR

CAR

LIR

RIER

RIIR

TTR

AER

FCR

TLR


INIR

RTC Initiation Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INIR INIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INIR

INIR : RTC Initiation (Write only) When RTC block is powered on, RTC is at reset state. User has to write a number (0x a5eb1357) to INIR to make RTC leaving reset state. Once the INIR is written as 0xa5eb1357, the RTC will be in un-reset state permanently. The INIR is a write-only field and read value will be always 0 . RTC Active Status (Read only)
bits : 0 - 31 (32 bit)
access : write-only

Enumeration:

0 : 0

RTC is at reset state

1 : 1

RTC is at normal active state

End of enumeration elements list.


CLR

Calendar Loading Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLR CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 _1DAY _10DAY _1MON _10MON _1YEAR _10YEAR

_1DAY : 1-Day Calendar Digit (0~9)
bits : 0 - 3 (4 bit)
access : read-write

_10DAY : 10-Day Calendar Digit (0~3)
bits : 4 - 5 (2 bit)
access : read-write

_1MON : 1-Month Calendar Digit (0~9)
bits : 8 - 11 (4 bit)
access : read-write

_10MON : 10-Month Calendar Digit (0~1)
bits : 12 - 12 (1 bit)
access : read-write

_1YEAR : 1-Year Calendar Digit (0~9)
bits : 16 - 19 (4 bit)
access : read-write

_10YEAR : 10-Year Calendar Digit (0~9)
bits : 20 - 23 (4 bit)
access : read-write


TSSR

Time Scale Selection Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TSSR TSSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 _24H_12H

_24H_12H : 24-Hour / 12-Hour Time Scale Selection\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Selected as 12-hour time scale with AM and PM indication

#1 : 1

Selected as 24-hour time scale

End of enumeration elements list.


DWR

Day of the Week Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DWR DWR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DWR

DWR : Day of the Week Register \n
bits : 0 - 2 (3 bit)
access : read-write


TAR

Time Alarm Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAR TAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 _1SEC _10SEC _1MIN _10MIN _1HR _10HR

_1SEC : 1-Sec Time Digit of Alarm Setting (0~9)
bits : 0 - 3 (4 bit)
access : read-write

_10SEC : 10-Sec Time Digit of Alarm Setting (0~5)
bits : 4 - 6 (3 bit)
access : read-write

_1MIN : 1-Min Time Digit of Alarm Setting (0~9)
bits : 8 - 11 (4 bit)
access : read-write

_10MIN : 10-Min Time Digit of Alarm Setting (0~5)
bits : 12 - 14 (3 bit)
access : read-write

_1HR : 1-Hour Time Digit of Alarm Setting (0~9)
bits : 16 - 19 (4 bit)
access : read-write

_10HR : 10-Hour Time Digit of Alarm Setting (0~2)
bits : 20 - 21 (2 bit)
access : read-write


CAR

Calendar Alarm Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAR CAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 _1DAY _10DAY _1MON _10MON _1YEAR _10YEAR

_1DAY : 1-Day Calendar Digit of Alarm Setting (0~9)
bits : 0 - 3 (4 bit)
access : read-write

_10DAY : 10-Day Calendar Digit of Alarm Setting (0~3)
bits : 4 - 5 (2 bit)
access : read-write

_1MON : 1-Month Calendar Digit of Alarm Setting (0~9)
bits : 8 - 11 (4 bit)
access : read-write

_10MON : 10-Month Calendar Digit of Alarm Setting (0~1)
bits : 12 - 12 (1 bit)
access : read-write

_1YEAR : 1-Year Calendar Digit of Alarm Setting (0~9)
bits : 16 - 19 (4 bit)
access : read-write

_10YEAR : 10-Year Calendar Digit of Alarm Setting (0~9)
bits : 20 - 23 (4 bit)
access : read-write


LIR

Leap Year Indicator Register
address_offset : 0x24 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LIR LIR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LIR

LIR : Leap Year Indication Register (Read Only)\n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

This year is not a leap year

#1 : 1

This year is leap year

End of enumeration elements list.


RIER

RTC Interrupt Enable Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RIER RIER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIER TIER

AIER : Alarm Interrupt Enable\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

RTC Alarm Interrupt Disabled

#1 : 1

RTC Alarm Interrupt Enabled

End of enumeration elements list.

TIER : Time Tick Interrupt Enable\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

RTC Time Tick Interrupt Disabled

#1 : 1

RTC Time Tick Interrupt Enabled

End of enumeration elements list.


RIIR

RTC Interrupt Indicator Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RIIR RIIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF TIF

AIF : RTC Alarm Interrupt Flag\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

RCT Alarm Interrupt condition never occurred

#1 : 1

RTC Alarm Interrupt is requested if RIER.AIER = 1

End of enumeration elements list.

TIF : RTC Time Tick Interrupt Flag\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

RCT Time Tick Interrupt condition never occurred

#1 : 1

RTC Time Tick Interrupt is requested if RIER.TIER = 1

End of enumeration elements list.


TTR

RTC Time Tick Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TTR TTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TTR TWKE

TTR : Time Tick Register\n
bits : 0 - 2 (3 bit)
access : read-write

TWKE : RTC Timer Wake-up Function Enable\nIf TWKE is set before chip is in Power-down mode, chip will be woken up by RTC controller when a RTC Time Tick occurs.\nNote1: Tick timer setting follows the TTR[2:0] description.\nNote2: When Alarm Match occurs, chip will be woken up from Power-down mode no matter TWKE is 1 or 0.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

RTC Timer wake-up Disabled by Timer Tick occur function

#1 : 1

RTC Timer wake-up function Enabled so that chip can be woken up from Power-down mode by Time Tick

End of enumeration elements list.


AER

RTC Access Enable Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AER AER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AER ENF

AER : RTC Register Access Enable Password (Write Only)\nWriting 0xA965 to this register will enable RTC access and keep 1024 RTC clock
bits : 0 - 15 (16 bit)
access : write-only

ENF : RTC Register Access Enable Flag (Read only)\n
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

#0 : 0

RTC register read/write Disabled

#1 : 1

RTC register read/write Enabled

End of enumeration elements list.


FCR

RTC Frequency Compensation Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FCR FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRACTION INTEGER

FRACTION : Fraction Part\nNote: Digit in FCR must be expressed as hexadecimal number. Refer to 5.8.4.4 for the examples.
bits : 0 - 5 (6 bit)
access : read-write

INTEGER : Integer Part\n
bits : 8 - 11 (4 bit)
access : read-write


TLR

Time Loading Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TLR TLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 _1SEC _10SEC _1MIN _10MIN _1HR _10HR

_1SEC : 1-Sec Time Digit (0~9)
bits : 0 - 3 (4 bit)
access : read-write

_10SEC : 10-Sec Time Digit (0~5)
bits : 4 - 6 (3 bit)
access : read-write

_1MIN : 1-Min Time Digit (0~9)
bits : 8 - 11 (4 bit)
access : read-write

_10MIN : 10-Min Time Digit (0~5)
bits : 12 - 14 (3 bit)
access : read-write

_1HR : 1-Hour Time Digit (0~9)
bits : 16 - 19 (4 bit)
access : read-write

_10HR : 10-Hour Time Digit (0~2)
bits : 20 - 21 (2 bit)
access : read-write



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